Compressing detected current and preceding instructions with the same operation code and operand patterns

ABSTRACT

A processor accesses memory storing a compressed instruction sequence that includes compression information indicating that an instruction that with respect to the preceding instruction, has identical operation code and operand continuity is compressed. The processor includes a fetcher that fetches a bit string from the memory and determines whether the bit string is a non-compressed instruction, where if so, transfers the given bit string and if not, transfers the compression information; and a decoder that upon receiving the non-compressed instruction, holds in a buffer, instruction code and an operand pattern of the non-compressed instruction and executes processing to set to an initial value, the value of an instruction counter that indicates a count of consecutive instructions having identical operation code and operand continuity, and upon receiving the compression information, restores the instruction code based on the instruction code held in the buffer, the instruction counter value, and the operand pattern.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of U.S. patent application Ser. No.13/481,221, filed May 25, 2012, which is based upon and claims thebenefit of priority of the prior Japanese Patent Application No.2011-123851, filed on Jun. 1, 2011, the entire contents of which areincorporated herein by reference.

FIELD

The embodiments discussed herein are related to a processor thatexecutes an instruction, a processor that compresses an instruction, acomputer product, a compression apparatus, and a compression method.

BACKGROUND

Conventionally, technologies have been disclosed that upon a compressiondetermination instruction, issue an exclusive instruction to transitionto a compression mode, and perform transition to a compression mode anda non-compression mode (see, for example, Japanese Laid-Open PatentPublication Nos. 2001-142696 and 2003-050696). During the compressionmode, these technologies use a memory address that is different fromthat of the instruction memory (called a dictionary address, which isstored in compressed instruction code), refer to the dictionary memory,and restore an instruction.

Further, technology has been disclosed that stores a portion of theprevious operation code and a portion of the operand, and bycompensating deficient portions of compressed code by the stored code,restore the compressed code (see, for example, Japanese Laid-Open PatentPublication No. 2004-355477). This technology, for example, when thesize of the instruction code is 32 bits, compresses the code to 16 bits.

Technology that compresses and curtails frequent no operationinstructions in Very Long Instruction Words (VLIWs) and thereby reducesthe instruction code size has been disclosed (for example, JapaneseLaid-Open Patent Publication No. H7-182169).

Nonetheless, with the technologies according to Japanese Laid-OpenPatent Publication Nos. 2001-142696 and 2003-050696, since the memorythat is called dictionary memory, which is also different from theinstruction memory, is used, a problem arises in that the number ofmemory accesses increases by the number of accesses to the dictionarymemory and power consumption increases.

With the technology according to Japanese Laid-Open Patent PublicationNo. 2004-355477, since a portion of the preceding instruction code hasto be stored for each instruction code, a problem arises in thatcompression efficiency is low. Further, with the technology according toJapanese Laid-Open Patent Publication No. H7-182169, only no operationinstructions can be compressed. Thus, the instruction code compressionefficiency is low and a problem arises in that curtailing of the memoryaccess frequency is not sufficient as compared to before compression.

SUMMARY

According to an aspect of an embodiment, a processor has access to amemory storing therein a compressed instruction sequence that includescompression information indicating that an instruction having operationcode identical to that of the preceding instruction and having operandcontinuity with the preceding instruction has been compressed. Theprocessor includes a fetcher that fetches a given bit string from thememory and determines whether the given bit string is a non-compressedinstruction, where upon determining the given bit string to be anon-compressed instruction, further transfers the given bit string andupon determining the given bit string to not be a non-compressedinstruction, further transfers the compression information located atthe head of the given bit string; and a decoder that upon receiving thenon-compressed instruction transferred thereto from the fetcher, holdsin a buffer, instruction code and an operand pattern of thenon-compressed instruction and executes setting processing of setting toan initial value, the value of an instruction counter that indicates aconsecutive count of consecutive instructions having identical operationcode and operands with regularity, and upon receiving the compressioninformation transferred thereto from the fetcher, restores theinstruction code based on the instruction code held in the buffer, thevalue of the instruction counter, and the operand pattern.

The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and arenot restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram depicting the flow of instruction compression andinstruction execution.

FIG. 2 is a diagram of the structure of an instruction IS.

FIG. 3 is a block diagram of a hardware configuration of a compressionapparatus according to a first embodiment.

FIG. 4 is a block diagram depicting an example of a functionalconfiguration of the compression apparatus according to a first example.

FIG. 5 is a diagram of an example of a storage determining table T.

FIG. 6 is a diagram depicting an example of compression processingaccording to the first example.

FIG. 7 is a first part of a flowchart depicting a procedure ofcompression processing by the compression apparatus according to thefirst example.

FIG. 8 is a second part of a flowchart depicting the compressionprocedure by the compression apparatus.

FIG. 9 is a diagram of one example of a sequence of instruction groupsaccording to a second example.

FIG. 10 is a block diagram depicting an example of a functionalconfiguration of the compression apparatus according to the secondexample.

FIGS. 11A, 11B, and 11C depict an example of compression processingaccording to the second example.

FIG. 12 is a flowchart depicting an example of a procedure ofcompression processing by the compression apparatus according to thesecond example.

FIG. 13 is a first part of a flowchart depicting an example of aprocedure of test-subject compression processing (step S1205) depictedin FIG. 12.

FIG. 14 is a second part of a flowchart of the example of the procedureof the test-subject compression processing (step S1205) depicted in FIG.12.

FIG. 15 is a block diagram depicting an example of a hardwareconfiguration of a processor depicted in FIG. 1.

FIG. 16 is a diagram of a first configuration example of an operandupdater.

FIG. 17 is a diagram of a second configuration example of the operandupdater.

FIG. 18 is a diagram of a third configuration example of the operandupdater.

FIG. 19 is a flowchart of processing by the processor.

FIGS. 20 to 36 are diagrams of an example of pipeline processingaccording to a third embodiment.

FIGS. 37 to 42 are diagrams of an example of recovery processing forrecovery from an interrupt.

FIGS. 43 to 55 are diagrams of an example of pipeline processingaccording to a fourth embodiment.

FIGS. 56 to 64 are diagrams of an example of recovery processing forrecovery from an interrupt.

DESCRIPTION OF EMBODIMENTS

Preferred embodiments of the present invention will be explained withreference to the accompanying drawings.

FIG. 1 is a diagram depicting the flow of instruction compression andinstruction execution. In the present embodiment, instruction sequencesare compressed by a compression program installed on a computer. Aninstruction sequence is a set of consecutive instructions, for example,stored in order of address in a storage device. In FIG. 1, as anexample, instructions IS1 to IS6 are regarded as an instructionsequence. For the sake of convenience, herein an instruction in aninstruction sequence is indicated as an “instruction IS”.

FIG. 2 is a diagram of the structure of an instruction IS. In FIG. 2,instruction IS1 is taken as an example. An instruction IS is informationwhere a compression bit and a storage bit are appended to operation codeand operands. As an example, the instruction width is assumed to be 32bits.

The compression bit is compression information that indicates whetherthe instruction IS is to be compressed. For example, when thecompression bit is “1”, compression is indicated and when thecompression bit is “0”, no-compression is indicated. Before compression,the compression bit is assumed to indicate no-compression (“0”). Thestorage bit is storage information that indicates whether theinstruction IS to be stored as a restoration source instruction. Forexample, when the storage bit is “1”, storage is indicated and when thestorage bit is “0”, no-storage is indicated. Before compression, thestorage bit is assumed to indicate no-storage (“0”).

In FIG. 1, a compression apparatus 101 is a computer on which acompression program is installed. The compression apparatus 101compresses instruction sequences ISs. The compression apparatus 101performs compression, when 2 instructions having consecutive addressesfurther have the same operation code and operands that have continuity.For example, both operation codes among the consecutive instructionsIS1, IS2 are ADD and the operands increase by 1. Consequently,instruction IS2 is compressed.

Similarly, the instruction IS3 is also compressed. Compression betweenthe instructions IS3 and IS4; the instructions IS4 and IS5; and theinstructions IS5 and IS6 is not performed. Further, with regard to theinstruction IS6, instruction IS5 is disregarded and consequent to therelation with the instruction IS4, compression is performed. Details ofthe compression are described hereinafter.

Furthermore, an instruction group that has been compressed by thecompression apparatus 101 is referred to as a compressed instructiongroup iss. A compressed instruction group iss includes both(non-compressed) instructions that are restoration sources andcompressed instructions that can be restored by referring to arestoration source instruction. A processor 102, by fetching acompressed instruction group iss, restores the compressed instructionsand executes the instructions. Details of the execution will bedescribed hereinafter. The processor 102 may be a central processingunit (CPU) in the compression apparatus 101 or may be a CPU of acomputer different from the compression apparatus 101. The processor 102may further be a digital signal processor (DSP).

A first embodiment will be described. In the first embodiment, theinstruction compression depicted in FIG. 1 will be described.

FIG. 3 is a block diagram of a hardware configuration of the compressionapparatus 101 according to the first embodiment. As depicted in FIG. 3,the compression apparatus 101 includes a CPU 301, a read-only memory(ROM) 302, a random access memory (RAM) 303, a magnetic disk drive 304,a magnetic disk 305, an optical disk drive 306, an optical disk 307, adisplay 308, an interface (I/F) 309, a keyboard 310, a mouse 311, ascanner 312, and a printer 313, respectively connected by a bus 300.

The CPU 301 governs overall control of the compression apparatus 101.The ROM 302 stores therein programs such as a boot program. The RAM 303is used as a work area of the CPU 301. The magnetic disk drive 304,under the control of the CPU 301, controls the reading and writing ofdata with respect to the magnetic disk 305. The magnetic disk 305 storestherein data written under control of the magnetic disk drive 304.

The optical disk drive 306, under the control of the CPU 301, controlsthe reading and writing of data with respect to the optical disk 307.The optical disk 307 stores therein data written under control of theoptical disk drive 306, the data being read by a computer.

The display 308 displays, for example, data such as text, images,functional information, etc., in addition to a cursor, icons, and/ortool boxes. A cathode ray tube (CRT), a thin-film-transistor (TFT)liquid crystal display, a plasma display, etc., may be employed as thedisplay 308.

The I/F 309 is connected to a network 314 such as a local area network(LAN), a wide area network (WAN), and the Internet through acommunication line and is connected to other apparatuses through thenetwork 314. The I/F 309 administers an internal interface with thenetwork 314 and controls the input/output of data from/to externalapparatuses. For example, a modem or a LAN adaptor may be employed asthe I/F 309.

The keyboard 310 includes, for example, keys for inputting letters,numerals, and various instructions and performs the input of data.Alternatively, a touch-panel-type input pad or numeric keypad, etc. maybe adopted. The mouse 311 is used to move the cursor, select a region,or move and change the size of windows. A track ball or a joy stick maybe adopted provided each respectively has a function similar to apointing device.

The scanner 312 optically reads an image and takes in the image datainto the compression apparatus 101. The scanner 312 may have an opticalcharacter reader (OCR) function as well. The printer 313 prints imagedata and text data. The printer 313 may be, for example, a laser printeror an ink jet printer.

Instructions include regular instructions and instruction groups thatinclude multiple instructions such as a VLIW. In a first example, a casewill be described where an instruction sequence that is subsequent to aregular instruction is compressed. In a second example, a case will bedescribed where a sequence of instruction groups subsequent to aninstruction group that includes multiple instructions, is compressed.

FIG. 4 is a block diagram depicting an example of a functionalconfiguration of the compression apparatus 101 according to the firstexample. The compression apparatus 101 includes an acquirer 401, adeterminer 402, a compressor 403, and a setter 404. These functions (theacquirer 401 to the setter 404) forming a controller, for example, arerealized by executing on the CPU 301, a program stored in a storagedevice such as the ROM 302, the RAM 303, the magnetic disk 305, and theoptical disk 307 depicted in FIG. 3, or by the I/F 309.

The acquirer 401 acquires a given instruction as a test subject fromamong an instruction sequence. For example, the acquirer 401 reads in aninstruction sequence such as that in FIG. 1, sequentially according toaddress, one instruction at a time. For example, beginning with theinstruction IS1 at the head address 0xF000, the acquirer 401 acquiresthe instructions in the sequence of IS1, IS2, IS3, IS4, IS5, IS6.

The determiner 402 determines whether the operation code of the testsubject acquired by the acquirer 401 and the operation code of theinstruction preceding the test subject are identical; and determineswhether operands of the test subject and operands of the precedinginstruction have continuity. The test subject is the instruction IS readin at the current reading. The preceding instruction is the instructionIS that was read in at the reading immediately preceding the currentreading. For example, if the test subject is the instruction IS2, thepreceding instruction is the instruction IS1. When the test subject isthe instruction IS1, there is no preceding instruction. Continuity amongoperands is a state in which like operands vary in a regular manner.

An operand pattern is embedded in the operation code. The operandpattern indicates the operand structure and includes the operand type,the operand count, and the starting position of the head operand. Forexample, in the case of the instruction IS1, the operand type isregister and the operand count is 3. Further, assuming that operationcode is 12 bits, the starting position of the head operand is the 15thbit from the head of the instruction IS1. This operand pattern, forexample, is assumed to be embedded in the upper bit string of theoperation code.

At the determiner 402, when the operand patterns of the test subject andof the preceding instruction are identical and the operand values areconsecutive, continuity is determined. When the operand patterns of thetest subject and of the preceding instruction are not identical,non-continuity is determined without checking the operand values.

For example, in the case of the instructions IS1, IS2, the operands ofthe instruction IS1 are r0, r16 and r32; and the operands of theinstruction IS2 are r1, r17 and r33. Thus, since the register addressesincrease by 1 between the instructions IS1 and IS2, the operands havecontinuity. “+1” indicating the increase by 1 is stored in a continuitybuffer. Similarly, between the instructions IS2 and IS3, and theinstructions IS1 and IS2, the register addresses increase by 1 and thecontinuity buffer values match. Therefore, the successive operands havecontinuity. When there is no continuity, the continuity buffer isinitialized.

In this manner, when the register numbers and memory addresses vary withcontinuity, there is continuity among operands. In the example depictedin FIG. 1, for the instructions IS1 to IS3, the operation codes aredetermined to be identical and continuity among the operands isdetermined.

When the storage bit of the test subject instruction IS is “0”(no-storage), the continuity buffer is maintained as is. For example,the instruction IS5 subsequent to the instruction IS4 is no operationinstruction (NOP) and as described hereinafter, the storage bit of theinstruction IS5 is set as “0”. In this case, when the instruction IS6 isrestored by the processor 102, since the storage bit of the instructionIS5 is “0” and is not restored, by further tracing back to theinstruction IS4, it is determined whether the operation codes of theinstructions IS4 and IS6 are identical and whether the operands havecontinuity.

Operand continuity is not limited to regular increases of the registernumbers and addresses, etc., and may be increments by a variable as wellas decrements. If the magnitude of increase/decrease is the same foreach instruction, the magnitude of increase/decrease need not be 1.Further, if the register numbers are the same, continuity is determinedbecause, for example, in the case of values set to specify aninstruction operation, the same register (register number) may bespecified. In this case, the magnitude of increase/decrease is 0. In thecase of immediate value as well, if the magnitude of increase/decreaseis the same, continuity is determined. Further, when changes are by aconstant rule (for example, corresponds to expressions depicted in FIG.16), continuity is determined. Additionally, when immediate values arethe same value, continuity is determined.

When identicalness and continuity are not determined, the determiner402, based on the operation code type of the test subject, may determinewhether the test subject is an instruction that is to be stored as arestoration source instruction. Among the instructions are systeminstructions without operands like HALT, RET, RFE, EXTW, and NOP. Suchsystem instructions are not used as restoration sources for compressedinstructions.

FIG. 5 is a diagram of an example of a storage determining table T. Asdepicted in FIG. 5, the storage determining table T includes a storageflag for each operation code. Thus, according to the operation code ofthe test subject, whether the test subject is to be stored as arestoration source instruction can be determined. For example, when theoperation code of the instruction IS1 is ADD, the storage flag is “1”(storage) and consequently, it is determined that the test subject is tobe stored as a restoration source instruction.

When the operation code of the test subject is HALT, the storage flag is“0” (no-storage) and consequently, it is determined that the testsubject is not to be stored as a restoration source instruction. Thestorage determining table T is stored in a storage device such as theROM 302, the RAM 303, the magnetic disk 305, and the optical disk 307depicted in FIG. 3.

The compressor 403, when identicalness and continuity have beendetermined by the determiner 402, compresses the test subject. Forexample, the compressor 403, when identicalness and continuity have beendetermined by the determiner, appends to the test subject, compressioninformation indicating that the test subject is to be compressed, anddeletes the instruction code in the test subject. For example, in thecase of compression, the compressor 403 sets the compression bit of thetest subject to “1” (compression), making the test subject a compressedinstruction. In other words, in the case of compression, the storage bitand the instruction code are completely deleted, leaving only thecompression bit. As a result, for example, an instruction of a given bitwidth (e.g., 32 bits, 64 bits, 128 bits, etc.) can be compressed to 1bit.

The setter 404, when non-identicalness and non-continuity have beendetermined by the determiner 402, sets for the test subject, compressioninformation indicating that the test subject is not to be compressed andstorage information indicating that the test subject is to be stored asan instruction not subject to compression. For example, whennon-identicalness and non-continuity have been determined by thedeterminer 402, the setter 404 sets the test subject to not be subjectto compression. Therefore, the setter 404 sets the compression bit ofthe test subject to “0” (no-compression). Further, since the testsubject is not to be compressed, the setter 404 sets the storage bit ofthe test subject to “1” (storage). As a result, when the subsequentinstruction is compressed, the non-compressed test subject becomes therestoration source of the subsequent instruction.

Further, when non-identicalness and non-continuity have been determinedby the determiner 402 and storage has been determined by the determiner402, the setter 404 sets, for test subject, compression informationindicating that the test subject is not to be compressed and furthersets storage information indicating that the test subject is to bestored as a restoration source instruction. For example, the setter 404sets the compression bit of the test subject to “0” (no-compression) andfurther sets the storage bit of the test subject to “1” (storage).Consequently, when the subsequent instruction is compressed, thenon-compressed test subject becomes the restoration source of thesubsequent instruction.

On the other hand, when non-identicalness, non-continuity, andno-storage are determined by the determiner 402, the setter 404 sets forthe test subject, information indicating that the test subject is not tobe compressed and further sets information indicating that the testsubject is not to be stored as a restoration source instruction. Forexample, the setter 404 sets the compression bit of the test subject to“0” (no-compression) and sets the storage bit of the test subject to “0”(no-storage), whereby the non-compressed test subject does not become arestoration source of the subsequent instruction.

FIG. 6 is a diagram depicting an example of compression processingaccording to the first example. FIG. 5 depicts an example of compressionof the instruction group depicted in FIG. 1. The compression apparatus101 reads in the instruction IS1 of address 0xF000. Since there is noinstruction preceding the instruction IS1, the compression bit of theinstruction IS1 is “0” (no-compression). Further, since the operationcode of the instruction IS1 is ADD, the storage bit of the instructionIS1 is “1” (storage). Thus, for the instruction IS1, after compression,the storage bit changes from “0” to “1”.

The instruction IS2 has the same operation code as the precedinginstruction IS1 and operand continuity. Consequently, the compressionbit becomes “1” and all else is deleted. The instruction IS3 has thesame operation code as the preceding instruction IS2 and operandcontinuity. Consequently, the compression bit becomes “1” and all elseis deleted.

The instruction IS4 does not have the same operation code as thepreceding instruction IS3. Consequently, the compression bit is set to“0”. Further, the operation code of the instruction IS4 is STORE andthus, the instruction IS4 is to be stored as a restoration sourceinstruction. Therefore, the storage bit is set to “1”. Hence, for theinstruction IS4, after compression, the storage bit changes from “0” to“1”.

The instruction IS5 does not have the same operation code as thepreceding instruction IS4. Consequently, the compression bit is set to“0”. Further, the instruction IS5 is a NOP instruction and thus, is notto be stored as a restoration source instruction. Therefore, the storagebit is set to “0”. Thus, for the instruction IS5, after compression, thesame command as before compression is stored.

The instruction IS6 does not have the same operation code as thepreceding instruction IS5, but the storage bit of the precedinginstruction IS5 is set to “0” and consequently, the instruction IS4 isregarded as the preceding instruction. In this case, the instruction IS6has the same operation code as the preceding instruction IS4 and operandcontinuity. Consequently, the compression bit of the instruction IS6becomes “1” and all else is deleted. In this manner, in the presentembodiment, the more consecutive test subjects having the same operationcode as the preceding instruction and operand continuity there are, thehigher the compression efficiency is. In this case, the updated operandbecomes 0x0001. However, depending on the data size and/or memory sizehandled by the instruction, the value of the instruction counter 14 maybe multiplied by a coefficient by a decoder block (156).

FIG. 7 is a first part of a flowchart depicting a procedure ofcompression processing by the compression apparatus 101 according to thefirst example. The compression apparatus 101 determines whether aninstruction is present in an instruction group (step S701). If noinstruction is present (step S701: NO), the compression processing ends.On the other hand, if an instruction is present (step S701: YES), thecompression apparatus 101, via the acquirer 401, acquires a test subject(step S702) and via the determiner 402, determines whether the testsubject has the same operation code as the preceding instruction (stepS703). A case where the operation codes are identical (step S703: YES)is described with in FIG. 8.

If the operation codes are not identical (step S703: NO), thecompression apparatus 101, via the determiner 402, refers to the storagebit of the preceding instruction and determines whether the precedinginstruction is an instruction that is not to be stored as a restorationsource instruction (step S704). If the preceding instruction is aninstruction that is not to be stored as a restoration source instruction(step S704: YES), the preceding instruction is a system instructionwithout an operand. Accordingly, the operation codes of the test subjectand of the instruction immediately before the preceding instruction (thepreceding instruction when the preceding instruction of the current testsubject was the test subject) may be identical and there may be operandcontinuity. Therefore, the compression apparatus 101, via the setter404, changes the preceding instruction to the instruction immediatelybefore the preceding instruction (step S705), and returns to step S703.

At step S705, for example, if the test subject is the instruction IS6depicted in FIG. 6, the preceding instruction is the NOP instructionIS5. Since an NOP is not to be stored as a restoration sourceinstruction, the instruction IS4, which was 1 instruction before thepreceding instruction IS5 (NOP), is regarded as the precedinginstruction.

If the preceding instruction is not an instruction that is not to bestored as a restoration source instruction (step S704: NO), i.e., is aninstruction to be stored as a restoration source instruction, thecompression apparatus 101, via the setter 404, initializes thecontinuity buffer (step S706), and sets the compression bit of the testsubject to “0” (step S707).

The compression apparatus 101, via the determiner 402, determineswhether the test subject is to be stored as a restoration sourceinstruction (step S708). For example, in the storage determining tableT, if the storage flag corresponding to the operation code of the testsubject is “1”, storage as a restoration source instruction isindicated; and if “0”, such storage is not indicated.

If the test subject is to be stored as a restoration source instruction(step S708: YES), the compression apparatus 101, via the setter 404,sets the storage bit of the test subject to “1” (step S709). Thecompression apparatus 101 stores to a compression buffer, anon-compressed instruction having a compression bit of “0”, a storagebit of “1”, an operation code identical to that of the test subject andoperands (step S710); and then, returns to step S701.

At step S708, if the test subject is not to be stored as a restorationsource instruction (step S708: NO), the compression apparatus 101, viathe setter 404, sets the storage bit of the test subject to “0” (stepS711). The compression apparatus 101 stores to the compression buffer, anon-compressed instruction having a compression bit of “0”, a storagebit of “0”, an operation code that is identical to that of the testsubject and operands (step S712). In other words, the compressionapparatus 101 stores the test subject as is and returns to step S701.

FIG. 8 is a second part of a flowchart depicting the compressionprocedure by the compression apparatus 101. At step S703 depicted inFIG. 7, if the operation codes are identical (step S703: YES), thecompression apparatus 101, via the determiner 402, determines whetherthe operand patterns of the preceding instruction of and of the testsubject are identical (step S801). If the operand patterns are notidentical (step S801: NO), the operands are not consecutive and the testsubject is excluded as a compression subject. Consequently, thecompression apparatus 101 transitions to step S706 depicted in FIG. 7,and via the setter 404, initializes the continuity buffer.

If the operand patterns are identical (step S801: YES), the compressionapparatus 101 detects differences between the operands of the precedinginstruction and the operands of the test subject (step S802). Forexample, when the preceding instruction is the instruction IS1 and thetest subject is the instruction IS2, the difference is “+1”. Similarly,when the preceding instruction is the instruction IS2 and the testsubject is the instruction IS3, the difference is “+1”.

The compression apparatus 101, via the determiner 402, determineswhether the detected difference and the value of the continuity bufferare identical (step S804). When the detected difference and thecontinuity buffer value are not identical (step S804: NO), thecontinuity buffer is initialized and the compression apparatus 101, viathe setter 404, updates the continuity buffer to the detected difference(step S803), and transitions to step S707.

When the detected difference and the continuity buffer value areidentical (step S804: YES), such as when the preceding instruction isthe instruction IS2 and the test subject is the instruction IS3, thecompression apparatus 101, via the compressor 403, sets the compressionbit of the test subject to “1” (step S805). Thereafter, the compressionapparatus 101, via the compressor 403, deletes the bit string (storagebit, instruction code) subsequent to the compression bit of the testsubject (step S806). Thus, the compression apparatus 101 stores to thecompression buffer, a compressed instruction that includes only thecompression bit (=1) (step S807), and transitions to step S701.

Thus, the compression apparatus 101 enables high compression of aninstruction group by compressing instructions (test subjects) that withrespect to the preceding instruction, have the same operation code andoperand continuity. For example, when there are M successive m-bitinstructions meeting the compression conditions, in an uncompressedstate, there are (mxM) bits. Whereas, after compression by thecompression apparatus 101, only the head instruction is not compressedand the subsequent instructions are compressed to 1 bit (i.e., thecompression bit).

Therefore, the compressed size becomes (m+M−1) bits. Thus, when the sizeis reduced by compression, since the maximum amount of compressedinstructions equivalent to the bus width can be fetched collectively,the number of accesses to the memory can be reduced and powerconsumption can be reduced. Further, system instructions such as NOPshave no operands and consequently, such instructions are not subject tostorage as a restoration source instruction, enabling the instructionsto be excluded from restoration sources and thereby, enablingimprovement of the restoration processing efficiency.

The second example will be described. In the second example, compressionof an instruction sequence group of consecutive instruction groupsexecuted in parallel such as a VLIW will be described.

FIG. 9 is a diagram of one example of a sequence of instruction groupsaccording to the second example. Here, a VLIW will be described as anexample. In a sequence of instruction groups Vs, multiple VLIWinstructions having multiple instructions (4 in FIG. 9) such as thosedepicted in FIG. 1 are present. Further, in the sequence of instructiongroups Vs, an instruction at the same position in each of theinstruction sequences is framed by a bold line. For example, in theinstruction sequence V1 to V4 of the sequence of instruction groups Vs,the head instruction A1 at address 0x0000, the head instruction A2 ataddress 0x0010, the head instruction A3 at address 0x0020, and the headinstruction A4 at address 0x0030 are instructions at the same position.Further, in the sequence of instruction groups Vs depicted in FIG. 9, asan example, 1 instruction has 32 bits as in the first example, and since1 group is assumed to be configured by a sequence of 4 instructions, 1group has 128 bits. The structure of the instruction is identical tothat depicted in FIG. 2.

FIG. 10 is a block diagram depicting an example of a functionalconfiguration of the compression apparatus 101 according to the secondexample. As depicted in FIG. 10, the compression apparatus 101 includesan acquirer 1001, a determiner 1002, a compressor 1003, a setter 1004,and a storer 1005. These functions (the acquirer 1001 to the setter1004) forming a controller, for example, are realized by executing onthe CPU 301, a program stored in storage device such as the ROM 302, theRAM 303, the magnetic disk 305, and the optical disk 307 depicted inFIG. 3, or by the I/F 309.

The acquirer 1001 acquires a given instruction as a test subject from aninstruction group under test, among the sequence of instruction groups.For example, from the head address 0x0000 of the sequence of instructiongroups, the acquirer 1001 sequentially acquires instruction groups V1,V2, V3, and V4. Further, when the instruction group V1 is acquired, theacquirer 1001 sequentially acquires an instruction A1, an instructionB1, an instruction C1, and an instruction D1. After the acquisition ofthe instruction D1, the instruction group V2 at the next address 0x0010is assumed to be acquired.

The determiner 1002 executes determination processing identical to thedeterminer 402 of the first example. However, in the second example,since instructions are handled in units of instruction groups, thepreceding instruction of the test subject is not the immediatelypreceding instruction, but rather the instruction at the same positionin the preceding instruction group. For example, the precedinginstruction of the instruction B2 at address 0x0010 is not theinstruction A1 at address 0x0010, but rather the instruction B1 at thesame position in the preceding instruction group V1. Further, thecompressor 1003 executes compression processing that is identical tothat of the compressor 403 of the first example.

The setter 1004 executes setting processing identical to the setter 404of the first example. However, similar to the determiner 1002, thepreceding instruction of the test subject is not the instructionimmediately preceding instruction, but rather the instruction at thesame position in the preceding instruction group. In the second example,a continuity buffer is set for each position of the instructions in theinstruction groups. For example, the instructions A1 to A4 are atdifferent positions in the instruction group and thus, a continuitybuffer is prepared for each position. In other words, in the exampledepicted in FIG. 9, 4 continuity buffers are set.

The storer 1005 stores a compression information group obtained from thetest subjects of the instruction group under test and subsequent to thecompression information group, further stores non-compressed testsubjects among the instruction group under test and for which storageinformation has been set. In the first example, compressed instructionsand non-compressed instructions are written to the compression buffersimply in the order of writing. However, in the second example, for eachinstruction group, the compression bits of the instructions in theinstruction group are collectively placed at the head. A string ofcompression bits collected in this manner is referred to as a“compression information group”.

The storer 1005 establishes an area for the compression informationgroup in the compression buffer, and from the head instruction of theinstruction group under test, writes the compression bits. When thecompression bit is “0” (no-compression), the non-compressed instructionincluding the storage bit, operation code, and operands is writtensubsequent to the compression information group.

In this manner, the storer 1005, for each instruction group, writes acompression information group and 0 or more non-compressed instructionsto the compression buffer. However, if even 1 instruction is compressedin the instruction groups, empty areas arise and by performing shiftsaccording to the empty areas, the compressed sequence of instructiongroups can be shortened. By such shortening, the number of fetchesperformed can be reduced, enabling increased processing speed at theprocessor 102 and reduced power consumption.

FIGS. 11A, 11B, and 11C are diagrams of an example of the compressionprocessing according to the second example. FIGS. 11A to 11C depict anexample where the sequence of instruction groups depicted in FIG. 9 iscompressed. FIG. 11A depicts the sequence of instruction groups beforecompression; FIG. 11B depicts the sequence of instruction groups aftercompression; and FIG. 11C depicts the compressed sequence of instructiongroups after shortening.

In FIG. 11A, the compression apparatus 101 reads in the instructiongroup V1 at address 0x0000, decodes the instruction group V1, and readsin the instruction A1. Since the instruction group V1 has no precedinginstruction group, the instruction A1 has no preceding instruction.Consequently, the compression bit of instruction A1 is “0”(no-compression). In FIG. 11B, the head bit of a compression informationgroup C1 of the instruction group V1 is set to “0”. Since theinstruction group V1 is the head instruction group, the subsequentinstructions B1, C1, D1 have the same results.

In FIG. 11A, the compression apparatus 101, upon completing thecompression processing for the instruction group V1 at address 0x0000,reads in (as the instruction group under test) the instruction group V2at the next address 0x0010, decodes the instruction group V2, and readsin the instruction A2. Since the preceding instruction group of theinstruction group V2 is the instruction group V1, the precedinginstruction of the instruction A2 is the instruction A1. Since theinstruction A2 satisfies the compression conditions (same operation codeand operand continuity) of the determiner 1002, the compressionapparatus 101 sets the compression bit of the instruction A2 to “1”(compression). Accordingly, as depicted in FIG. 11B, the head bit of acompression information group C2 of the instruction group V1 is set to“1”, and the storage bit, the operation code, and the operands aredeleted. The subsequent instructions B2, C2, and D2 of the instructiongroup V2 have the same results.

For the instruction group V3 at address 0x0020, the instructions A3 andC3 are compressed, while the instructions F and NOP are not. Similarly,for the instruction group V4 at address 0x0030, the instructions A4 andD3 are compressed, while the instructions B3 and NOP are not. Althoughthe preceding instruction of the instruction D3 is the NOP of theinstruction group V3, in the case of an NOP, since the continuity bufferholds the difference of the instruction therebefore (i.e., theinstruction D2), the instruction D3 is compressed.

By shortening the state depicted in FIG. 11B to the state depicted inFIG. 11C, the shortened sequence of compressed instruction groups sys isstored at addresses 0xF100 to 0xF120, where address 0xF130 is an emptyarea. Accordingly, in the state depicted in FIG. 11A, assuming the buswidth is 128, 4 memory accesses are required. However, in the statedepicted in FIG. 11C, the memory access count is 3, thereby enabling areduction of the memory access count.

FIG. 12 is a flowchart depicting an example of a procedure ofcompression processing by the compression apparatus 101 according to thesecond example. The compression apparatus 101 determines whether aninstruction group is present in a sequence of instruction groups (stepS1201). If an instruction group is present (step S1201: YES), thecompression apparatus 101, via the acquirer 1001, acquires aninstruction group as an instruction group under test (step S1202); andestablishes in the compression buffer, a compression information grouparea of N-bits, where N=the number of instructions in the instructiongroup under test (in the example depicted in FIG. 9, N=4) (step S1203).The compression apparatus 101 sets an index i, which indicates theposition of the instruction in the instruction group under test, as i=1(step S1204). In the example depicted in FIG. 9, from the left i=1, 2,3, 4(=N).

Subsequently, the compression apparatus 101 executes test-subjectcompression processing (step S1205). In the test-subject compressionprocessing (step S1205), compression processing of the test subject,which is the i-th instruction of the instruction group under test, isexecuted. Contents of the compression processing are described withreference to FIGS. 13 and 14.

When the test-subject compression processing (step S1205) is executed,the compression apparatus 101 increments i (step S1206), and determineswhether i>N is true (step S1207). If i>N is not true (step S1207: NO),the compression apparatus 101 returns to the test-subject compressionprocessing (step S1205). On the other hand, if i>N is true (step S1207:YES), the compression apparatus 101 returns to step S1201.

At step S1201, if no instruction group is present (step S1201: NO), thecompression apparatus 101, via the storer 1005, bit-shifts thecompressed instruction group stored in the compression buffer, andthereby shortens the compressed instruction group (the bit-shiftingbeing performed according to the empty areas as depicted in FIG. 11C)(step S1208), ending the compression processing.

FIG. 13 is a first part of a flowchart depicting an example of aprocedure of the test-subject compression processing (step S1205)depicted in FIG. 12. In FIG. 13, the compression apparatus 101, via thedeterminer 1002, determines whether test subject has the same operationcode as the preceding instruction (step S1301). If the operation code isthe same (step S1301: YES), the processing described with reference toFIG. 14 is performed.

On the other hand, if the operation code is not the same (step S1301:NO), the compression apparatus 101, via the determiner 1002, refers tothe storage bit of the preceding instruction, and determines whether thepreceding instruction is an instruction that is not to be stored as arestoration source instruction (step S1302). If the precedinginstruction is an instruction that is not to be stored as a restorationsource instruction (step S1302: YES), the preceding instruction is asystem instruction without operands and consequently, the test subjectand the instruction at the same position in the instruction group beforethe instruction group preceding the instruction group under test mayhave the same operation code and operand continuity. Therefore, thecompression apparatus 101, via the setter 1004, changes the precedinginstruction to the instruction at the same position in the instructiongroup therebefore (step S1303), and returns to step S1301.

For example, if the test subject is the instruction D3 depicted in FIG.11A, the preceding instruction is an NOP of the instruction group V3.Since an NOP is not stored as a restoration instruction, the instructionD2 at the same position in the instruction group V2, which is theinstruction group before that of the preceding instruction (NOP), isregarded as the preceding instruction.

Further, if the preceding instruction is not an instruction that is notto be stored as a restoration source (step S1302: NO), i.e., is aninstruction to be stored as a restoration source instruction, thecompression apparatus 101, via the setter 1004, initializes thecontinuity buffer of the i-th position (step S1304), and sets thecompression bit of the test subject to “0” (step S1305).

The compression apparatus 101, via the determiner 1002, determineswhether the test subject is an instruction that is to be stored as arestoration source instruction (step S1306). For example, thecompression apparatus 101 refers to the storage determining table T andif the storage flag concerning the operation code for the test subjectis “1”, determines that the instruction is to be stored and if “0”,determines that the instruction is not to be stored as a restorationresource instruction.

If the instruction is to be stored as a restoration source instruction(step S1306: YES), the compression apparatus 101 sets the storage bit ofthe test subject to “1” (step S1307). The compression apparatus 101, viathe storer 1005, stores the compression bit “0” to the i-th bit positionin the compression information group area in the compression buffer.Further, for storage bits of “1”, the compression apparatus 101, via thestorer 1005, stores subsequent to the compression information group inthe compression buffer, the operation code and operands that areidentical to those of the test subject (step S1308). Thus, anon-compressed instruction concerning the test subject is stored and thecompression apparatus 101 returns to step S1206.

At step S1306, if the instruction is not to be stored as a restorationsource instruction (step S1306: NO), the compression apparatus 101 setsthe storage bit of the test subject to “0” (step S1309). The compressionapparatus 101 stores the compression bit “0” to the i-th bit position inthe compression information group area of the compression buffer. Forstorage bits of “0”, the compression apparatus 101 stores subsequent tothe compression information group in the compression buffer, theoperation code and operands that are identical to those of the testsubject (step S1310). Thus, a non-compressed instruction concerning thetest subject is stored and the compression apparatus 101 returns to stepS1206.

FIG. 14 is a second part of a flowchart of the example of the procedureof the test-subject compression processing (step S1205) depicted in FIG.12. In FIG. 14, when the operation code is the same at step S1301depicted in FIG. 13 (step S1301: YES), the compression apparatus 101,via the determiner 1002, determines whether the operand patterns of thepreceding instruction and the test subject are identical (step S1401).If the operand patterns are not identical (step S1401: NO), the operandshave no continuity and the test subject is not be subject tocompression. Therefore, the compression apparatus 101 transitions tostep S1304 in FIG. 12 and via the setter 1004, initializes the i-thposition continuity buffer.

On the other hand, if the operand patterns are identical (step S1401:YES), the compression apparatus 101 detects differences between theoperands of the preceding instruction and the operands of the testsubject (step S1402). For example, in the case of the precedinginstruction A1 and the test subject instruction A2, the difference is“+1”. Similarly, in the case of the preceding instruction A2 and thetest subject instruction A3, the difference is “+1”.

The compression apparatus 101, via the determiner 1002, determineswhether the detected difference and the continuity buffer value areidentical (step S1403). When the detected difference and the i-thposition continuity buffer value are not identical (step S1403: NO), thecompression apparatus 101 updates the i-th position continuity buffer tothe detected difference (step S1404) and transitions to step S1305.

When the detected difference and the i-th position continuity buffervalue are identical (step S1403: YES), such as in the case of thepreceding instruction A2 and the test subject instruction A3, thecompression apparatus 101, via the compressor 1003, sets the compressionbit of the test subject to “1” (step S1405). The compression apparatus101, via the compressor 1003, deletes the bit string (storage bit,instruction code) subsequent to the compression bit of the test subject(step S1406), whereby the compression apparatus 101 stores to the i-thposition of the compression information group area of the compressionbuffer, a compressed instruction formed of merely the compression bit(=1) (step S1407). Thereafter, the compression apparatus 101 transitionsto step S1206.

Thus, by compressing a test subject that, with respect to the precedinginstruction, has the same operation code and operand continuity, thecompression apparatus 101 enables high compression of a sequence ofinstruction groups. For example, M consecutive instruction groups of Ninstructions of m-bits and satisfying the compression conditions, is(m×N×m) bits in a non-compressed state; whereas, subsequent tocompression by the compression apparatus 101, the head instruction groupalone is not subject to compression and the instructions of thesubsequent instruction group are compressed to 1 bit (compression bit).

Consequently, the compressed size becomes (m×N+(M−1)×N) bits. Thus, whenthe size is reduced by compression, since the maximum amount ofcompressed instructions equivalent to the bus width can be fetchedcollectively, the number of accesses to the memory can be reduced andpower consumption can be reduced. Further, system instructions such asNOPs have no operands and consequently, such instructions are notsubject to storage as a restoration source instruction, enabling theinstructions to be excluded from restoration sources and thereby,enabling improvement of the restoration processing efficiency.

A second embodiment will be described. In the second embodiment, theinstruction execution depicted in FIG. 1 will be described. In thesecond embodiment, the processor 102 depicted in FIG. 1, while readingin an instruction sequence, performs execution processes concerningnon-compressed instructions; and for compressed instructions, restoreseach instruction by referring to the restoration source instruction andexecutes the instruction. In this manner, by fetching a compressedinstruction sequence, the number of fetches performed, i.e., the numberof memory access can be reduced and power consumption can be reduced.

FIG. 15 is a block diagram depicting an example of a hardwareconfiguration of the processor 102 depicted in FIG. 1. The processor 102is connected to an instruction RAM 151 and a data RAM 152, via a bus,enabling access thereto. The bus width, for example, is assumed to be 32bits. The instruction RAM 151 stores therein the compressed instructionsequence iss depicted in FIG. 6, the compressed instruction sequencegroup vs depicted in FIG. 11B, or the compressed instruction sequencegroup sys depicted in FIG. 11C. The processor 102 is further connectedto other surrounding modules (not depicted) such as an input apparatus,an output apparatus, a communication apparatus, a DSP, another CPU,enabling access respectively thereto.

The processor 102 includes a controller 153, a recovery register group154, a fetch controller 155, a decoder 156, an executing unit 157, amemory access unit 158, a data register 159, and an interrupt controller1510.

The controller 153 is connected to the interrupt controller 1510, thefetch controller 155, the decoder 156, the executing unit 157, thememory access unit 158, the recovery register group 154, and the dataregister 159 (hereinafter, collectively referred to as “connectiondestinations”). The controller 153 controls the connection destinations,and transfers data from a given connection destination to anotherconnection destination. Further, the controller 153 controls a pipelinebetween the fetch controller 155, the decoder 156, the executing unit157, and the memory access unit 158.

The recovery register group 154 is configured by an upper recoveryregister 1541, an intermediate recovery register 1542, and a lowerrecovery register 1543 connected in series. The upper recovery register1541 is connected to the fetch controller 155 and the decoder 156; theintermediate recovery register 1542 is connected to the executing unit157; and the lower recovery register 1543 is connected to the memoryaccess unit 158.

The recovery registers respectively include a program counter 11, 21,31; an instruction buffer 12, 22, 32; a bit field information (BFI)register 13, 23, 33; and an instruction counter 14, 24, 34. The programcounters 11, 21, 31 hold therein values that are counted by the fetchcontroller 155 and transferred from upstream. The instruction buffers12, 22, 32 hold therein instruction codes obtained by the decoder 156.The BFI registers 13, 23, 33 hold therein the operand patterns of theinstruction codes obtained by the decoder 156. The instruction counters14, 24, 34 indicate the number of consecutive times that the operationcodes are identical and the operands are regularly consecutive. Thevalue held by the upper recovery register 1541 is taken on by theintermediate recovery register 1542; the value held by the intermediaterecovery register 1542 is taken on by the lower recovery register 1543.

The fetch controller 155 includes a prefetch buffer 1551, a fetch buffer1552, and a program counter 1553. Here, the bit width of the prefetchbuffer 1551 and the fetch buffer 1552 is equivalent to the bus width.The fetch controller 155 prefetches from the instruction RAM 151, dataof the bus width and stores the data to the prefetch buffer 1551.

When the fetch buffer 1552 has empty areas, the fetch controller 155sequentially transfers to the fetch buffer 1552, data that remains inthe prefetch buffer 1551, the transferring being from the head data(first in, first out). When the head bit of the data held by the fetchbuffer 155 is “0” (i.e., compression bit=0), the fetch controller 155determines the instruction to be a non-compressed instruction. In thiscase, the fetch controller 155 transfers to the decoder 156, a bitstring of a number of bits equivalent to the non-compressed instruction.

On the other hand, when the head bit of the data held in the fetchbuffer 1552 is “1” (i.e., compression bit=1), the fetch controller 155determines the instruction to be a compressed instruction. In this case,the fetch controller 155 transfers to the decoder 156, bits of a numberequivalent to the compressed instruction (the bit value is compressioninformation=“1”, indicating compression).

The program counter 1553 counts the position of the compressedinstruction sequence fetched from the instruction RAM 151. For example,at the fetch controller 155, if a non-compressed instruction isdetermined, the program counter 1553 increments the value of the programcounter 1553 by the bit length of the non-compressed instruction (forexample, in the case of 32 bits, by 32). On the other hand, at the fetchcontroller 155, if a compressed instruction is determined, the programcounter 1553 increments the value of the program counter 1553 by the bitlength of the compressed instruction (for example, in the case of 1, by1).

When data is transferred from the fetch buffer 1552, the fetchcontroller 155 shifts the remaining data toward the head. When the fetchbuffer 1552 is empty, the fetch controller 155 fetches data equivalentto the bit width of the prefetch buffer 1551. When the value of theprogram counter 1553 is updated, the fetch controller 155 transfers tothe upper program counter 11, the updated value of the program counter1553.

The decoder 156 is connected to the upper recovery register 1541 in therecovery register group 154, enabling access thereto. The upper recoveryregister 1541 includes the upper program counter 11, the upperinstruction buffer 12, the upper BFI register 13, and the upperinstruction counter 14. When the value of the program counter 1553 inthe fetch controller 155 is updated and transferred, the decoder 156updates the value of the upper program counter 11 to the updated valueof the program counter 1553.

The decoder 156 interprets the instruction transferred from the fetchcontroller 155 and passes the instruction to the executing unit 157. Theinstruction transferred from the fetch controller 155 includes 2 types,a non-compressed instruction and a compressed instruction. For example,when the head bit of data transferred from the fetch controller 155 is“0” (i.e., compression bit=0), the decoder 156 determines theinstruction to be a non-compressed instruction. On the other hand, whenthe head bit of data transferred from the fetch controller 155 is “1”(i.e., compression bit=1), the decoder determines the instruction to bea compressed instruction.

If the transferred instruction is determined to be a non-compressedinstruction, the decoder 156 extracts the instruction code from thenon-compressed instruction and transfers the extracted instruction codeto the executing unit 157. For example, if the instruction IS1 ataddress 0xF100 and depicted in FIG. 5 is transferred, the instructioncode (operation code ADD, operands r0, r16, r32) excluding the head 2bits “01” is transferred to the executing unit 157.

If the transferred instruction is determined to be a non-compressedinstruction, the decoder 156, according to the storage bit, which is thesecond bit from the head, determines whether storage to the upperinstruction buffer 12 is to be performed with respect to the transferredinstruction. If the instruction is determined to not be subject tostorage (storage bit=0), storage to the upper instruction buffer 12 andthe upper BFI register 13 is not performed.

On the other hand, if the transferred instruction is determined to besubject to storage, the decoder 156 interprets the operand pattern ofthe instruction code and writes the operand pattern to the upper BFIregister 13. For example, if the operand pattern is written to the upperbit of the operation code, the operand pattern is written to the upperBFI register 13. For example, in the case of the instruction IS1 ataddress 0xF100 and depicted in FIG. 6, the operand pattern written tothe upper BFI register 13 is information indicating that the type ofoperand is register, the operand count is 3, the starting position ofthe head operand is the 15th bit from the head of the instruction code.

Further, if the transferred instruction is to be subject to storage, thedecoder 156 writes the instruction code to the upper instruction buffer12. For example, if the instruction IS1 at address 0xF100 and depictedin FIG. 6 is transferred, the instruction code (operation code ADD,operands r0, r16, r32) exclusive of the head 2 bits “01”, is written tothe upper instruction buffer 12.

Further, if the transferred instruction is determined to be subject tostorage, the decoder 156 sets the instruction counter to the initialvalue. For example, the decoder 156 sets the initial value as 1. Theinstruction counter is incremented by 1 each time a compressedinstruction is transferred, and returns to the initial value if anon-compressed instruction is transferred.

Further, if the transferred instruction is determined to be a compressedinstruction, the decoder 156, for example, in the case of 1-bitcompression information, restores the instruction to the originalinstruction based on the current values of the upper BFI register 13,the upper instruction buffer 12, and the upper instruction counter 14.For example, if the head bit (left end) “1” at address 0xF120 depictedin FIG. 6 is transferred, the instruction code (operation code ADD andoperands r1, r17, r33) in the instruction IS2 is restored.

Similarly, if the second bit “1” from the head (left end) at address0xF120 depicted in FIG. 6 is transferred, the instruction code(operation code ADD and operands r2, r18, r34) in the instruction IS3 isrestored. Details of the restoration processing will be describedhereinafter. The decoder 156 transfers the restored instruction to theexecuting unit 157. If the decoder 156 has restored an instruction,after transferring the instruction to the executing unit 157, thedecoder increments the instruction counter by 1.

If a non-compressed instruction or a restored instruction is transferredto the executing unit 157, the decoder 156 transfers the values of theupper recovery register 1541 to the intermediate recovery register 1542,whereby the values of the intermediate recovery register 1542 areupdated, enabling the instruction code transferred to the executing unit157 and the values of the intermediate recovery register 1542 to besynchronized.

The executing unit 157 executes the instruction code transferred theretofrom the decoder 156 and writes the instruction code to the dataregister 159 specified by the operands. The executing unit 157 transfersthe instruction code to the memory access unit 158. Here, the executingunit 157, via the controller 153, transfers each value in theintermediate recovery register 1542 to the lower recovery register 1543.As a result, the values of the lower recovery register 1543 are updated,enabling the instruction code transferred to the memory access unit 158and the value of the lower recovery register 1543 to be synchronized.

If the instruction code transferred from the executing unit 157 includesthe address of the data RAM 152, which is the access destination, thememory access unit 158 accesses the data RAM 152. For example, if theoperation code of the transferred instruction code is LOAD, data is readin from the address of the data RAM 152 indicated in the instructioncode and is written to the data register 159 specified by the operand.If the operation code of the transferred instruction code is STORE, thevalue of the data register 159 specified by the data operand is writtento the data RAM 152 address indicated in the instruction code.

The interrupt controller 1510 detects an interrupt signal from asurrounding module. The interrupt controller 1510 informs the controller153 of the detected interrupt signal, whereby the controller 153preferentially causes execution of the interrupting instruction withrespect to the fetch controller 155, the decoder 156, the executing unit157 and the memory access unit 158. In this case, the memory access unit158 causes the values of the lower recovery register 1543 to be saved ina stack area 1520 of the data RAM 152.

The interrupt controller 1510 detects an interrupt processing completionsignal from a surrounding module. The interrupt controller 1510 informsthe controller 153 of the detected interrupt signal, whereby thecontroller 153 causes, with respect to the fetch controller 155, thedecoder 156, the executing unit 157, and the memory access unit 158, theexecution of recovery processing for recovering the state before theinterrupt. For example, the instruction code at the time of theinterrupt at the memory access unit 158 is recovered at the decoder 156by using the values of the lower register, stored to the stack area 1520of the data RAM 152. The recovery processing of restoring the statebefore an interrupt will be described in detail hereinafter.

An operand updater in the decoder 156 will be described in detail.According to the operand pattern held in the upper the BFI register 13,the operand updater extracts the operands held in the upper instructionbuffer 12, 1 operand at a time. From the extracted operands and thevalue of the instruction counter, the operand updater updates theextracted operands. The contents of the updating processing, forexample, are as follows.

Operand=Operand OP X  (1)

X=IC or (IC OP K)  (2)

OP=+ or − or * or / or >> or <<  (3)

Where, K=coefficient

In equation 1, the left-hand term “Operand” is the updated operand, theright-hand term “Operand” is the operand before updating. In equations 1and 2, “OP” is an operation, and as prescribed by equation 3, is anarithmetic operator and a shift operation is performed. “X” is avariable and “IC” is the value of the upper instruction counter 14. “X”is the value “IC” of the upper instruction counter 14 or a valueresulting from an operation involving a constant K and the value “IC” ofthe upper instruction counter 14.

For example, when the operand (register number, variable) increases by 1for each instruction, the value of the instruction counter increases by1, whereby “OP” is OP=“+”, and X=IC is set. As a result, equation 1becomes as follows.

Operand=Operand+IC  (4)

When the operand (register number, variable) increases by 2 for eachinstruction, the value of the instruction counter increases by 1,whereby “OP” is OP=“+”, and K=1 is set. As a result, equation 1 becomesas follows.

Operand=Operand+IC+1  (5)

When the operand (register number, variable) decreases by 1 for eachinstruction, the value of the instruction counter increases by 1,whereby in equation 2, OP=“*” and K=−1 is set, and in equation 1, “OP”is set as OP=“+”. As a result, equation 1 becomes as follows.

Operand=Operand+{IC*(−1)}  (6)

The way that the operand regularly changes for each instruction, i.e.,concerning the combination of “OP” and “K”, is specified by theinstruction code. Such circuit configuration can be built fromcombinational circuits. Hereinafter, an example will be described indetail.

FIG. 16 is a diagram of a first configuration example of the operandupdater. In FIG. 16, an operand updater 1600 is configured by equationsA to Z, an equation setting register 1601, a coefficient register 1602,and a selector 1603. Each of the equations A to Z is configured bycombinational circuits. When there is an equation changing instruction,equation-setting code that selects any equation from among the equationsA to Z is written to the equation setting register 1601. When there is acoefficient changing instruction, a value K is written to thecoefficient register 1602.

In each of the equations A to Z, the operand before updating (right-handterm Operand of equation 1), the value IC of the upper instructioncounter 14, and the value K of the coefficient register 1602 are input.The equation-setting code written in the equation setting register 1601is input to the selector 1603. Output from the selector is the updatedoperand (left-hand term Operand of equation 1).

For example, as a non-compressed instruction, an equation changinginstruction and a coefficient changing instruction are in the compressedinstruction sequence depicted in FIG. 6, at the address before 0xF100;the value of the operand (selection code specifying the equation to beused from among the equations A to Z) of the equation changinginstruction is held in the equation setting register 1601; and the valueK=0 of the operand of the coefficient changing instruction is held inthe coefficient register 1602.

For example, in the case of the instruction IS1 at 0xF100, equation A isassumed to be equation 4. The selection code of equation A is held inthe equation setting register 1601. As a result, the value IC of theinstruction counter, the register number r0, which is the operand beforeupdating, and the coefficient K=0 are input, and according to equation4, the updated operand becomes r1. The same is true concerning r16 andr32.

FIG. 17 is a diagram of a second configuration example of the operandupdater 1600. FIG. 16 depicts an example where an equation changinginstruction and a coefficient changing instruction are included in acompressed instruction sequence. FIG. 17 depicts an example where theoperation code (or a portion thereof) of a restoration sourceinstruction is the selection code of the equations A to Z. For example,when the operation code is ADD, selection code selecting equation A isset. When the operation code is STORE, selection code selecting equationB is set by a selector 1703. In such a configuration, instructionsequivalent to the equation changing instructions become unnecessary,enabling efficient compression to be facilitated.

FIG. 18 is a diagram of a third configuration example of the operandupdater 1600. FIG. 18 depicts an example of a configuration enablingselection of an equation setting method of setting any one among theconfiguration example depicted in FIG. 16 and the configuration exampledepicted in FIG. 17. Since the configuration example depicted in FIG. 16can be selected, the configuration example can be selected even in acase where the operation codes differ and the operations are the same.

For example, the operand updater 1600 includes an equation settingmethod selection register 1801, and selectors 1802, 1803. When there isan equation-setting method changing instruction, selection codeselecting any one of the operation code and the equation-setting codewritten in the equation setting register, is written in the equationsetting method selection register 1801. According to the selection codewritten in the equation setting method selection register 1801, aselector 1802 selects any one among the operation code and theequation-setting code written in the equation setting register.According to a selection signal from the selector 1802, a selector 1803selects the corresponding equation from among the equations A to Z andupdates the operand. In each of the configuration examples depicted inFIGS. 16 to 18, the operand updater 1600 can handle the regular changesof the operands, for each instruction.

FIG. 19 is a flowchart of processing by the processor 102. The processor102, via the fetch controller 155, performs prefetching (step S1901) andfetching (step S1902). The processor 102, via the fetch controller 155,refers to the head bit of the fetch buffer, and determines whether a bitstring in the fetch buffer is a compressed instruction or anon-compressed instruction (step S1903). If the bit string is anon-compressed instruction (step S1903: NO), the processor 102, via theprefetch buffer 1551, increments the value of the program counter by thenumber of non-compressed instructions (step S1904).

Thereafter, the processor 102, via the decoder 156, determines whetherthe non-compressed instruction is to be stored as a restoration sourceinstruction (step S1905). For example, the processor 102 refers to thestorage bit (the second bit from the head) and if the storage bit is“1”, determines that the non-compressed instruction is to be stored as arestoration source instruction, and if the storage bit is “0”,determines that the non-compressed instruction is not to be stored as arestoration source instruction.

If the non-compressed instruction is not to be stored as a restorationsource instruction (step S1905: NO), the processor 102, via the decoder156, decodes the non-compressed instruction (step S1906) and transitionsto step S1914. On the other hand, if the non-compressed instruction isto be stored as a restoration source instruction (step S1905: YES), theprocessor 102, via the decoder 156, stores to the upper instructionbuffer 12, the instruction code in the non-compressed instruction (stepS1907). Thereafter, the processor 102, via the decoder 156, decodes thenon-compressed instruction (step S1908), stores the operand pattern ofthe non-compressed instruction to the upper BFI register 13, initializesthe upper instruction counter 14 (step S1909), and transitions to stepS1914.

At step S1903, if the bit string is a compressed instruction (stepS1903: YES), the processor 102, via the fetch controller 155, incrementsthe value of the program counter by the number of compressedinstructions (step S1910). The processor 102, via the decoder 156,acquires the instruction code held in the upper instruction buffer 12(step S1911).

Thereafter, the processor 102 acquires the operand pattern from theupper BFI register 13 and thereby, identifies the operand to be updatedand based on the value of the upper instruction counter 14, updates eachof the operands to be updated, via the operand updater 1600 (stepS1912). The processor 102, via the decoder 156, combines the operationcode in the instruction code acquired from the upper instruction buffer12 and the updated operand; and thereby, restores the compressedinstruction to the instruction before compression (step S1913). Theprocessor 102 transitions to step S1914.

The processor 102, at step S1914, determines whether the bit length ofthe bit string prefetched by the fetch controller 155 is at least agiven size (step S1914), and if the bit length is the given size orgreater (step S1914: YES), returns to step S1902 and performs fetching(step S1902).

On the other hand, if the bit length is not the given size or greater(step S1914: NO), the processor 102 returns to step S1901 and performsprefetching (step S1901). Thus, by the operation of the fetch controller155 and the decoder 156, a non-compressed instruction is normallydecoded and transferred to the executing unit 157; and a compressedinstruction is restored to the original instruction and transferred tothe executing unit 157.

Pipeline processing according to the second embodiment will bedescribed. In the pipeline processing, instruction fetching by the fetchcontroller 155, register read by the decoder 156, execution by theexecuting unit 157, and memory access by the memory access unit (stagebefore commit) are executed. In the pipeline processing, as describedabove, at the register read stage by the decoder 156, the operand isupdated, the instruction code before compression is restored, andrecovery processing in the case of an interrupt is executed. In a thirdembodiment, pipeline processing of a compressed instruction sequencecompressed by the first example will be described; and in a fourthembodiment, pipeline processing of a sequence of compressed instructiongroups compressed by the second example will be described.

FIGS. 20 to 36 are diagrams of an example of pipeline processingaccording to the third embodiment. In FIG. 20, the fetch controller 155prefetches and holds in the prefetch buffer 1551, the bit string(instruction IS1) at address 0xF100 of the instruction RAM 151.

In FIG. 21, the fetch controller 155 fetches from the prefetch buffer1551 and holds in the fetch buffer, the bit string (instruction IS1) ofaddress 0xF100 of the instruction RAM 151. The fetch controller 155,prefetches and holds in the prefetch buffer 1551, which has become emptyconsequent to the fetching, the bit string at address 0xF104 of theinstruction RAM 151.

In FIG. 22, the fetch controller 155 determines whether the bit string(instruction IS1) of address 0xF100 and held in the fetch buffer is anon-compressed instruction. For example, the fetch controller 155determines whether the head bit of the fetch buffer (compression bit) is“0” (no-compression) or “1” (compression). In the case of the bit stringof address 0xF100, since the head bit is “0”, the bit string of address0xF100 is determined to be a bit string of a non-compressed instruction.In this case, the fetch controller 155 transfers the entire bit stringin the fetch buffer to the decoder 156.

The fetch controller 155 updates the program counter by the number oftransferred bits. In this case, since the transferred bit string is 32bits, the value of the program counter becomes “32”. The fetchcontroller 155 transfers the updated value “32” of the program counterto the upper program counter 11 of the decoder 156.

The decoder 156, upon receiving the non-compressed instructiontransferred from the fetch controller 155, refers to the storage bit,which is the second bit from the head of non-compressed instruction. Inthis case, since the value of the storage bit is “1” (storage), thedecoder 156 holds in the upper instruction buffer 12, the instructioncode ISC1 (operation code: ADD, operand: r0, r16, r32) in thenon-compressed instruction. The decoder 156 holds the operand pattern D1of the instruction code ISC1 in the upper BFI register 13. The decoder156, since a non-compressed instruction has been transferred thereto,sets the upper instruction counter 14 to the initial value of “1”. Thedecoder 156 sets the program counter value transferred from the fetchcontroller 155 as the value of the upper program counter 11.

In FIG. 23, the fetch controller 155 fetches from the prefetch buffer1551 and holds in the fetch buffer 1552 that has become empty, the bitstring of address 0xF104. The fetch controller 155 prefetches and holdsin the prefetch buffer 1551, which has become empty consequent to thefetching, the bit string at address 0xF10C in the instruction RAM 151.

The decoder 156 transfers the instruction code ISC1 and the values ofthe upper recovery register 1541 to the executing unit 157. Theexecuting unit 157 updates the intermediate recovery register 1542 tothe values of the upper recovery register 1541. By referring to the dataregister 159 and the data RAM 152, the executing unit 157 executes theinstruction code ISC1 transferred from the decoder 156.

In FIG. 24, the fetch controller 155 determines whether the bit stringof address 0xF104 and held in the fetch buffer is a non-compressedinstruction. In the case of the bit string of address 0xF104, since thehead bit is “1”, the head bit of the bit string of address 0xF104 is acompressed instruction. In this case, the fetch controller 155 transfersthe head bit (=1) of the fetch buffer to the decoder 156.

The fetch controller 155 updates the program counter by the number oftransferred bits. In this case, since the transferred bit string is thehead bit (1 bit), the value of the program counter becomes “33”. Thefetch controller 155 transfers the updated value “33” of the programcounter to the upper program counter 11 of the decoder 156.

The decoder 156, upon receiving the compressed instruction transferredfrom the fetch controller 155, reads out the instruction code ISC1 heldin the upper instruction buffer 12, the operand pattern D1 held in theBFI register, and the value “1” of the instruction counter. The decoder156, via the operand updater 1600, updates the operands of the readinstruction code ISC1, whereby, the decoder 156 restores the originalinstruction code ISC2 (operation code: ADD, operands: r1, r17, r33).

The executing unit 157 transfers the instruction code ISC1 and thevalues of the intermediate recovery register 1542 to the memory accessunit 158. The memory access unit 158 updates the lower recovery register1543 to the values of the intermediate recovery register 1542. Thememory access unit 158 accesses the data RAM 152, according to theoperation code of the transferred instruction code. In the case of theinstruction code ISC1, since the data RAM 152 address is not in theoperands, the data RAM 152 is not accessed.

In FIG. 25, the decoder 156 transfers the restored instruction code ISC2and the values of the upper recovery register 1541 to the executing unit157. The decoder 156, after the transfer, increments the value of theupper instruction counter 14 by 1. The executing unit 157 updates theintermediate recovery register 1542 to the values of the upper recoveryregister 1541. Accordingly, the values of the upper recovery register1541 and the values of the intermediate recovery register 1542 onlydiffer for the value “2” of the upper instruction counter 14 and thevalue “1” of the intermediate counter 24. By referring to the dataregister 159 and the data RAM 152, the executing unit 157 executes theinstruction code ISC2 transferred from the decoder 156.

In FIG. 26, since 1 bit has become empty consequent to the transfer ofthe 1-bit compressed instruction as depicted in FIG. 24, the fetchcontroller 155 shifts the bit string (31 bits) remaining in the fetchbuffer by 1 bit, and fetches and holds in the empty area (1 bit), thehead bit of the prefetch buffer 1551. At the memory access unit 158,when the instruction code ISC1 is processed, processing (writeback)other than commit stage processing is performed.

In FIG. 27, the fetch controller 155 determines whether the bit stringin the fetch buffer is a non-compressed instruction. In the case of thisbit string, since the head bit is “1”, the head bit of the bit stringheld in the fetch buffer is determined to be a compressed instruction.In this case, the fetch controller 155 transfers the head bit (=1) inthe fetch buffer to the decoder 156.

The fetch controller 155 updates the program counter by the number oftransferred bits. In this case, since the transferred bit string is thehead bit (1 bit), the value of the program counter becomes “34”. Thefetch controller 155 transfers the updated program counter value “34” tothe upper program counter 11 of the decoder 156.

The decoder 156, upon receiving the compressed instruction transferredfrom the fetch controller 155, reads out the instruction code ISC1 heldin the upper instruction buffer 12, the operand pattern D1 held in theBFI register, and the instruction counter value “2”. The decoder 156,via the operand updater 1600, updates the operands of the readinstruction code ISC1, whereby the decoder 156 restores the originalinstruction code ISC3 (operation code: ADD, operands: r2, r18, r34).

The executing unit 157 transfers the instruction code ISC2 and the valueof the intermediate recovery register 1542 to the memory access unit158. The memory access unit 158 updates the lower recovery register 1543to the values of the intermediate recovery register 1542. The memoryaccess unit 158 accesses the data RAM 152, according to the operationcode of the transferred instruction code. In the case of the instructioncode ISC2, since the data RAM 152 address is not included in theoperands, the data RAM 152 is not accessed.

In FIG. 28, the decoder 156 transfers the restored instruction code ISC3and the value of the upper recovery register 1541 to the executing unit157. The decoder 156, after the transfer, increments the value of theupper instruction counter 14 by 1. The executing unit 157 updates theintermediate recovery register 1542 to the values of the upper recoveryregister 1541. Accordingly, the values of the upper recovery register1541 and the values of the intermediate recovery register 1542 onlydiffer for the value of “3” for the upper instruction counter 14 and thevalue of “2” for the intermediate instruction counter 24. By referringto the data register 159 and the data RAM 152, the executing unit 157executes the instruction code ISC3 transferred from the decoder 156.

In FIG. 29, since 1 bit has become empty consequent to the transfer ofthe 1-bit compressed instruction as depicted in FIG. 28, the fetchcontroller 155 shifts the bit string (31 bits) remaining in the fetchbuffer by 1 bit, and fetches and holds in the empty area (1 bit), thehead bit of the prefetch buffer 1551. At the memory access unit 158,when the instruction code ISC2 is processed, processing (writeback)other than commit stage processing is performed.

In FIG. 30, the fetch controller 155 determines whether the bit stringin the fetch buffer is a non-compressed instruction. In the case of thisbit string, since the head bit is “0”, the bit string in the fetchbuffer 1552 is determined to be a bit string of a non-compressedinstruction. In this case, the fetch controller 155 transfers the entirebit string in the fetch buffer to the decoder 156.

The fetch controller 155 updates the program counter 1553 by the numberof bits transferred. In this case, since the transferred bit string is32 bits, the value of the program counter 1553 becomes “66”. The fetchcontroller 155 transfers the updated program counter value “66” to theupper program counter 11 of the decoder 156.

The decoder 156, upon receiving the non-compressed instructiontransferred from the fetch controller 155, refers to the storage bit,which is the second bit from the head of the non-compressed instruction.In this case, since the value of the storage bit is “1” (storage), theinstruction code ISC4 (operation code: STORE, operands: r32, 0x0000) inthe non-compressed instruction are held in the upper instruction buffer12. The decoder 156 holds the operand pattern D4 of the instruction codeISC4 in the upper BFI register 13. The decoder 156, since anon-compressed instruction has been transferred thereto, sets theinstruction counter 14 to the initial value of “1”. The decoder 156 setsthe program counter value “66” transferred thereto from the fetchcontroller 155, as the upper program counter 11 value “66”.

In FIG. 31, the fetch controller 155 fetches the 30-bit bit string inthe prefetch buffer 1551 (see FIG. 30). The fetch controller 155prefetches and holds in the prefetch buffer 1551, which has becomeempty, the bit string “001” at address 0xF160 in the instruction RAM151. Since 2 bits have become empty in the fetch buffer, the fetchcontroller 155 fetches and holds in the fetch buffer, the first 2 bits“00” among the 3 bits in prefetch buffer. As a result, the instructionIS5 is fetched and held in the fetch buffer.

The decoder 156 transfers the instruction code ISC4 and the value of theupper recovery register 1541 to the executing unit 157. The executingunit 157 updates the intermediate recovery register 1542 to the valuesof the upper recovery register 1541. By referring to the data register159 and the data RAM 152, the executing unit 157 executes theinstruction code ISC4 transferred from the decoder 156. At the memoryaccess unit 158, when the instruction code ISC3 is processed, processing(writeback) other than commit stage processing is performed.

In FIG. 32, the fetch controller 155 determines whether the bit string(instruction IS5) of address 0xF160 and held in the fetch buffer 1552 isa non-compressed instruction. In the case of the bit string of address0xF160, since the head bit is “0”, the bit string of address 0xF160 isdetermined to be a bit string of a non-compressed instruction(instruction IS5). In this case, the fetch controller 155 transfers theentire bit string (instruction IS5) in the fetch buffer 1552 to thedecoder 156.

The fetch controller 155 updates the program counter by the number oftransferred bits. In this case, since the transferred bit string is 32bits, the program counter value becomes “98”. The fetch controller 155transfers the updated program value “98” to the upper program counter 11of the decoder 156.

The decoder 156, upon receiving the non-compressed instructiontransferred from the fetch controller 155, refers to the storage bit,which is the second bit from the head of the non-compressed instruction(instruction IS5). In this case, since the value of the storage bit is“0” (no-storage), the instruction code ISC5 (NOP) in the non-compressedinstruction is not held in the upper instruction buffer 12. Similarly,the operand pattern of the instruction code ISC5 (NOP) is not held inthe upper BFI register 13.

Thus, for system instruction code such as the instruction code ISC5(NOP), by excluding system instruction code from operand updatingprocessing, operands can be updated from the value of the upper recoveryregister 1541 and the subsequent instruction code. The decoder 156,since a non-compressed instruction has been transferred thereto, setsthe upper instruction counter 14 to the initial value of “1”. Thedecoder 156 sets the program counter value “98” from the fetchcontroller 155, as the upper program counter 11 value “98”.

The executing unit 157 transfers the instruction code ISC4 and the valueof the intermediate recovery register 1542 to the memory access unit158. The memory access unit 158 updates the lower recovery register 1543to the values of the intermediate recovery register 1542. The memoryaccess unit 158 accesses the data RAM 152, according to the operationcode of the transferred instruction code. In the case of the instructioncode ISC4, since the data RAM 152 address 0x0000 is in the operands, thedata RAM 152 address 0x0000 is accessed (STORE).

In FIG. 33, the fetch controller 155 fetches and holds in the fetchbuffer 1552, which has become empty, the bit string (1 bit) in theprefetch buffer 1551. The decoder 156 transfers the instruction codeISC5 and the values of the upper recovery register 1541 to the executingunit 157. The executing unit 157 updates the intermediate recoveryregister 1542 to the values of the upper recovery register 1541. Theexecuting unit 157, since the instruction code ISC5 transferred from thedecoder 156 is NOP, does nothing. At the memory access unit 158, whenthe instruction code ISC4 is processed, processing (writeback) otherthan commit stage processing is performed.

In FIG. 34, the fetch controller 155 determines whether the bit stringin the fetch buffer 1552 is a non-compressed instruction. In the case ofthis bit string, since the head bit is “1”, the head bit of the bitstring held in the fetch buffer 1552 is determined to be a compressedinstruction. In this case, the fetch controller 155 transfers the headbit (=1) in the fetch buffer 1552 to the decoder 156.

The fetch controller 155 updates the program counter 1553 by the numberof transferred bits. In this case, since the transferred bit string isthe head bit (1 bit), the value of the program counter 1553 becomes“99”. The fetch controller 155 transfers the updated program counter1553 value “99” to the upper program counter 11 of the decoder 156.

The decoder 156, upon receiving the compressed instruction transferredfrom the fetch controller 155, reads out the instruction code ISC4 heldin the upper instruction buffer 12, the operand pattern D4 held in theupper BFI register 13, and the value “1” of the instruction counter 14.The decoder 156, via the operand updater 1600, updates the operand ofthe read instruction code ISC4, whereby the decoder 156 restores theoriginal instruction code ISC6 (operation code: STORE, operands: r33,0x0001). In this case, the updated operand becomes 0x0001. However,depending on the data size and/or memory size handled by theinstruction, the value of the instruction counter 14 may be multipliedby a coefficient by the decoder block (156).

The executing unit 157 transfers the instruction code ISC5 (NOP) and thevalues of the intermediate recovery register 1542 to the memory accessunit 158. The memory access unit 158 updates the lower recovery register1543 to the values of the intermediate recovery register 1542. Thememory access unit 158 accesses the data RAM 152, according to thetransferred operation code of the instruction code. In the case ofinstruction code ISC5, since the instruction code is NOP nothing isdone.

In FIG. 35, the decoder 156 transfers the restored instruction code ISC6and the value of the upper recovery register 1541 to the executing unit157. The decoder 156, after the transfer, increments the value of theupper instruction counter 14 by 1. The executing unit 157 updates theintermediate recovery register 1542 to the values of the upper recoveryregister 1541. Accordingly, the values of the upper recovery register1541 and the values of the intermediate recovery register 1542 differfor the value “2” of the upper instruction counter 14 and the value “1”of the intermediate counter 24. By referring to the data register 159and the data RAM 152, the executing unit 157 executes the instructioncode ISC6 transferred from the decoder 156.

In FIG. 36, the executing unit 157 transfers the instruction code ISC6and the values of the intermediate recovery register 1542 to the memoryaccess unit 158. The memory access unit 158 updates the lower recoveryregister 1543 to the values of the intermediate recovery register 1542.The memory access unit 158 accesses the data RAM 152, according to theoperation code of the transferred instruction code. In the case of theinstruction code ISC6, since the data RAM 152 address 0x0001 is in theoperands, the data RAM 152 address 0x0001 is accessed (STORE). At thememory access unit 158, when the instruction code ISC6 is processed,processing (writeback) other than commit stage processing is performed.

Thus, the compressed instruction sequence iss is pipeline processed,whereby the compressed instruction is restored by the decoder 156.Accordingly, the processor 102 can execute the same instructions as theinstruction sequence before compression. Further, since the compressedinstruction sequence iss includes compressed instructions, the number offetches from the instruction RAM 151 can be reduced. In other words,since the number of memory access to the instruction RAM 151 is reduced,reduced power consumption can be facilitated.

Recovery processing from an interrupt occurring during the instructionexecution depicted in FIGS. 20 to 36, will be described. When aninterrupt occurs, the processor 102 completes commit state transitionprocessing (writeback, . . . ) and then performs interrupt processing.In this case, concerning the commit pre-stage processing, the processor102 temporarily saves the value of the lower recovery register 1543 andexecutes the interrupt processing. When the interrupt processing ends,the processor 102 uses the saved value of the lower recovery register1543 and resumes the commit pre-stage processing. Hereinafter, a casewhere an interrupt occurs during the processing depicted in FIG. 31 willbe described with reference to FIGS. 37 to 42.

FIGS. 37 to 42 are diagrams of an example of recovery processing forrecovery from an interrupt. The processor 102, via the interruptcontroller 1510, detects the occurrence of an interrupt by a surroundingmodule or a timer and upon doing so, issues via the controller 153, aninterrupt signal to the fetch controller 155, the decoder 156, theexecuting unit 157, and the memory access unit 158.

In FIG. 37, the memory access unit 158, upon receiving the interruptsignal, saves the value of the lower recovery register 1543 or the valueof a generic register to the stack area 1520 of the data RAM 152.

In FIG. 38, the fetch controller 155, upon receiving the interruptsignal, clears the prefetch buffer 1551 and the fetch buffer 1552, andprepares for interrupt processing. Similarly, the decoder 156, theexecuting unit 157, the memory access unit 158, upon receiving theinterrupt signal, respectively clear the values of the upper recoveryregister 1541, the intermediate recovery register 1542, and the lowerrecovery register 1543, and prepare for interrupt processing. Theprocessor 102 executes the interrupt processing.

In FIG. 39, the decoder 156, upon receiving an interrupt completionsignal through the interrupt controller 1510 and the controller 153,sets the lower instruction buffer 32 value (instruction code ISC1) savedin the stack area 1520, the lower BFI register 33 value (operand patternD1), and the lower instruction counter 34 value “2” to the value of theupper instruction buffer 12, the value of the upper BFI register 13, andthe value of the upper instruction counter 14, respectively. The fetchcontroller 155 again clears the prefetch buffer 1551 and the fetchbuffer 1552, and reads in the lower program counter 31 value “34” savedin the stack area 1520.

In FIG. 40, the fetch controller 155 divides the lower program counter31 value “34” read from the stack area 1520 by the bit width (32 bits)of the fetch buffer. In this case, the quotient is “1” with a remainderof “2”. The fetch controller 155 multiplies the quotient “1” by the bitwidth (32 bits) of the fetch buffer and thereby, identifies the bitposition to be prefetched. In this case, since the quotient “1”×32bits=32, the bit string from the 32nd bit from the head of thecompressed instruction sequence, i.e., the bit string of address 0xF104of the instruction RAM 151 is prefetched and held in the prefetch buffer1551. The fetch controller 155 sets the program counter 1553 to “32”.

In FIG. 41, the fetch controller 155 determines whether the bit stringin the fetch buffer 1552 is a non-compressed instruction. In the case ofthis bit string, since the head bit is “1”, the head bit of the fetchedbit string is determined to be a compressed instruction. In this case,the fetch controller 155 transfers the head bit in the fetch buffer 1552to the decoder 156.

The fetch controller 155 updates the program counter 1553 by the numberof bits transferred. In this case, since the transferred bit string is 1bit, the value of the program counter 1553 becomes “33”. In this case,since this value and the lower program counter 31 value “34” saved inthe stack area 1520 do not coincide, the fetch controller 155 does nottransfer the updated program counter value “33” to the upper programcounter 11 of the decoder 156.

The decoder 156, despite having received the compressed instructiontransferred from the fetch buffer 1552, discards the compressedinstruction since the value of the program counter 1553 is not received.Thus, until the value of the program counter 1553 of the fetchcontroller 155 and the lower program counter 31 value read from thestack area 1520 coincide, the decoder 156 discards the bit strings fromthe fetch buffer 1552. As a result, at an errant bit position, theinstruction is not restored.

In FIG. 42, since 1 bit was transferred at the processing depicted inFIG. 40, the fetch controller 155 fetches the head bit of the prefetchbuffer 1551. Subsequently, the fetch controller 155 determines whetherthe bit string in the fetch buffer 1552 is a non-compressed instruction.In the case of this bit string, since the head bit is “1”, the head bitof the fetched bit string is determined to be a compressed instruction.In this case, the fetch controller 155 transfers the head bit in thefetch buffer 1552 to the decoder 156.

The fetch controller 155 updates the program counter 1553 by the numberof transferred bits. In this case, since the transferred bit string is 1bit, the value of the program counter 1553 becomes “34”. In this case,the fetch controller 155 transfers the updated program counter 1553value “34” to the upper program counter 11 of the decoder 156.

The decoder 156, having received the compressed instruction from thefetch buffer 1552 and the value of the program counter 1553, restoresthe instruction from the values of the upper recovery register 1541.Thus, the instruction code ISC2 that was processed up to the memoryaccess unit 158 at the time of the interrupt is restored. The processinghereinafter is executed similarly to that depicted in FIGS. 28 to 36.Thus, at the proper recovery position, the instruction can be restored.

The fourth embodiment will be described. In the fourth embodiment, anexample where instruction execution is performed concerning the sequenceof compressed instruction groups sys depicted in FIG. 11C will bedescribed. In the case of a sequence of compressed instruction groupssys, 1 instruction group (a non-compressed instruction group or arestored instruction group) includes N instructions (in FIG. 11A, N=4).Accordingly, the upper instruction buffer 12, the intermediate BFIregister 22, and the lower instruction buffer 32 hold therein a valuefor each instruction. Further, in the fourth embodiment, the bit widthof the prefetch buffer 1551 and the fetch buffer 1552 is assumed to be,for example, 128 bits.

FIGS. 43 to 55 are diagrams of an example of pipeline processingaccording to the fourth embodiment. In FIG. 43, the fetch controller 155prefetches and holds in the prefetch buffer 1551, the bit string ataddress 0xFF00 in the instruction RAM 151.

In FIG. 44, the fetch controller 155 fetches and holds in the fetchbuffer, the bit string that is of address 0xFF00 of the instruction RAM151 and that is in prefetch buffer 1551. The fetch controller 155further prefetches and holds in the prefetch buffer 1551 that has becomeempty consequent to the fetching, the bit string at address 0xFF10 inthe instruction RAM 151.

In FIG. 45, the fetch controller 155 determines whether the fetched bitstring of address 0xFF00 and held in the fetch buffer 1552 is anon-compressed instruction. For example, when the first 4 bits(compression bit string) of the fetch buffer 1552 are respectively “0”,the fetch controller 155 determines no-compression and when the first 4bits are respectively “1”, fetch controller 155 determines compression.In the case of the bit string at address 0xFF00, since the first 4 bitsare each “0”, the bit string of address 0xFF00 is determined to be a bitstring of 4 non-compressed instructions. In this case, the fetchcontroller 155 transfers the entire bit string in the fetch buffer 1552to the decoder 156.

The fetch controller 155 updates the program counter 1553 by the numberof transferred bits. In this case, since the transferred bit string is128 bits, the value of the program counter 1553 becomes “128”. The fetchcontroller 155 transfers the updated program counter value “128” to theupper program counter 11 of the decoder 156.

The decoder 156, upon receiving the non-compressed instruction grouptransferred from the fetch controller 155, divides the non-compressedinstruction group into 4 instructions. The decoder 156 refers to thestorage bit (the head bit) of each resulting non-compressed instruction.In this case, since the value of the storage bit of each of thenon-compressed instructions is “1” (storage), the decoder 156 holds inthe upper instruction buffer 12, each of the instruction codes A1 to D1in the non-compressed instructions.

The decoder 156 further holds in the upper BFI register 13, the operandpatterns A1-BFI to D1-BFI of the instruction codes A1 to D1. The decoder156, having received the non-compressed instructions A1 to D1, sets theinstruction counter 14 for each to the initial value of “1”. The decoder156 sets the program counter value transferred from the fetch controller155 as the upper program counter 11 value.

In FIG. 46, the fetch controller 155 fetches from the prefetch buffer1551 and holds in the fetch buffer 1552, which has become empty, the bitstring of address 0xFF10. The fetch controller 155 fetches and holds inthe prefetch buffer 1551 that has become empty consequent to thefetching, the bit string at address 0xFF20 in the instruction RAM 151.

The decoder 156 transfers the instruction codes A1 to D1 and the valueof the upper recovery register 1541 to the executing unit 157. Theexecuting unit 157 updates the intermediate recovery register 1542 tothe value of the upper recovery register 1541. By referring to the dataregister 159 and the data RAM 152, the executing unit 157 executes theinstruction codes A1 to D1 transferred from the decoder 156.

In FIG. 47, the fetch controller 155 determines whether the bit stringof address 0xFF10 and held in the fetch buffer 1552 is a non-compressedinstruction. In the case of the bit string of address 0xFF10, since thefirst 4 bits are each “1”, the first 4 bits of the bit string of address0xFF10 are determined to be a compressed instruction sequence. In thiscase, the fetch controller 155 transfers the first 4 bits (=1111) in thefetch buffer 1552 to the decoder 156.

The fetch controller 155 updates the program counter by the number ofbits transferred. In this case, since the transferred bit string is thefirst 4 bits, the value of the program counter becomes “132”. The fetchcontroller 155 transfers the updated program counter value “132” to theupper program counter 11 of the decoder 156.

In FIG. 48, since 4 bits have become empty consequent to the transfer ofthe 4 compressed instruction sequences as depicted in FIG. 47, the fetchcontroller 155 shifts the bit string (124 bits) remaining in the fetchbuffer by 4 bits, and fetches and holds in the empty area (4 bits), thefirst 4 bits of the prefetch buffer 1551.

The decoder 156, upon receiving the compressed instruction sequencesfrom the fetch controller 155, reads out for each instruction, theinstruction codes A1 to D1 held in the upper instruction buffer 12, theoperand patterns A1-BFI to D1-BFI held in the BFI register, and theinstruction counter value “1”. The decoder 156, via the operand updater1600, updates the operands of the instruction codes A1 to D1 for eachinstruction code, whereby the decoder 156 restores the originalinstruction codes A2 to D2.

The executing unit 157 transfers the instruction codes A1 to D1 and thevalues of the intermediate recovery register 1542 to the memory accessunit 158. The memory access unit 158 updates the lower recovery register1543 to the values of the intermediate recovery register 1542. Thememory access unit 158 further accesses the data RAM 152, according tothe operation code of the transferred instruction codes A1 to D1.

In FIG. 49, the decoder 156 transfers the restored instruction codes A2to D2 and the value of the upper recovery register 1541 to the executingunit 157. The decoder 156, after the transfer, increments the upperinstruction counters 14 by 1. The executing unit 157 updates theintermediate recovery register 1542 to the values of the upper recoveryregister 1541. Accordingly, the values of the upper recovery register1541 and the values of the intermediate recovery register 1542 differfor only the upper instruction counter 14 value “2” and the intermediateinstruction counter 24 value “1”. By referring to the data register 159and the data RAM 152, the executing unit 157 executes the instructioncodes A2 to D2 transferred from the decoder 156.

In FIG. 50, the fetch controller 155 determines whether the bit stringin the fetch buffer 1552 is a non-compressed instruction group. In thecase of this bit string, since the first 4 bits are “1010”, the firstbit and the third bit of the bit string held in the fetch buffer 1552are determined to be compressed instructions. The second instruction isa non-compressed instruction concatenated to a bit string “1 F” that issubsequent to the first 4 bits. The fourth instruction is anon-compressed instruction concatenated to a bit string “0 NOP” that issubsequent to the first 4 bits.

The fetch controller 155 updates the program counter 1553 by the numberof transferred bits. In this case, since the transferred bit string is66 bits, the value of the program counter 1553 becomes “198”. The fetchcontroller 155 transfers the updated program counter 1553 value “198” tothe upper program counter 11 of the decoder 156. At the memory accessunit 158, when the instruction codes A1 to D1 are processed, processing(writeback) other than the commit state processing is performed.

In FIG. 51, the fetch controller 155 performs a shift of 66 bits (thenumber of bits transferred to the decoder 156) toward the head. Thedecoder 156, with respect to the first and the third instructions, usesthe values of the upper instruction buffer 12, the upper BFI register13, and the upper instruction counter 14 to restore the originalinstructions A3, sC3. Further, with respect to the second and the fourthinstructions, the decoder 156 refers to storage bits. The storage bit inthe second instruction is “1” and thus, the decoder 156 updates thevalues of the upper instruction buffer 12, the upper BFI register 13,and the upper instruction counter 14.

The storage bit in the fourth instruction is “0” and thus, the decoder156 does not update the values of the upper instruction buffer 12, theupper BFI register 13, and the upper instruction counter 14 with respectto the instruction code NOP.

The executing unit 157 transfers the instruction codes A2 to D2 and thevalue of the intermediate recovery register 1542 to the memory accessunit 158. The memory access unit 158 updates the lower recovery register1543 to the value of the intermediate recovery register 1542. The memoryaccess unit 158 further accesses the data RAM 152, according to theoperation code of the transferred instruction code.

In FIG. 52, the decoder 156 transfers the instruction codes A3, F, C3,NOP and the value of the upper recovery register 1541 to the executingunit 157. The decoder 156, after the transfer, in the upper instructioncounter 14, increments by 1, the first and third instruction countervalues used in the operand updating. The executing unit 157 updates theintermediate recovery register 1542 to the values of the upper recoveryregister 1541. By referring to the data register 159 and the data RAM152, the executing unit 157 executes the instruction codes A3, F, C3,NOP transferred from the decoder 156.

In FIG. 53, the fetch controller 155 determines whether the bit stringin the fetch buffer 1552 is a non-compressed instruction group. In thecase of this bit string, since the first 4 bits are “1001”, the firstand the fourth bits of the bit string held in the fetch buffer 1552 aredetermined to be compressed instructions. The second instruction is anon-compressed instruction concatenated to a bit string “1 B3” that issubsequent to the first 4 bits. The third instruction is anon-compressed instruction concatenated to a bit string “0 NOP” that issubsequent to the first 4 bits.

The fetch controller 155 updates the program counter 1553 by the numberof transferred bits. In this case, since the transferred bit string is66, the value of the program counter 1553 becomes “264”. The fetchcontroller 155 transfers the updated program counter 1553 value “264” tothe upper program counter 11 of the decoder 156. At the memory accessunit 158, when the instruction codes A2 to D2 are processed, processing(writeback) other than the commit state processing is performed.

In FIG. 54, the decoder 156, with respect to the first and the fourthcompressed instructions, uses the values of the upper instruction buffer12, the upper BFI register 13, and the upper instruction counter 14 torestore the original instructions A4, D3. With respect to the second andthe third instructions, the decoder 156 refers to storage bits. Sincethe storage bit in the second instruction is “1”, the decoder 156updates the values of the upper instruction buffer 12, the upper BFIregister 13, and the upper instruction counter 14.

Further, since the storage bit in the third instruction is “0”, thedecoder 156 does not update the values of the upper instruction buffer12, the upper BFI register 13, and the upper instruction counter 14,with respect to the third instruction code NOP.

The executing unit 157 transfers the instruction codes A3, F, C3, NOPand the value of the intermediate recovery register 1542 to the memoryaccess unit 158. The memory access unit 158 updates the lower recoveryregister 1543 to the value of the intermediate recovery register 1542.The memory access unit 158 accesses the data RAM 152, according to theoperation code of the transferred instruction code.

In FIG. 55, the decoder 156 transfers the instruction codes A3, F, C3,NOP and the value of the upper recovery register 1541 to the executingunit 157. The decoder 156, after the transfer, in the upper instructioncounter 14, increments by 1, the first and the fourth valuescorresponding to the compressed instructions. The executing unit 157updates the intermediate recovery register 1542 to the values of theupper recovery register 1541. By referring to the data register 159 andthe data RAM 152, the executing unit 157 executes the instruction codesA3, F, C3, NOP transferred from the decoder 156.

Thus, by pipeline processing a sequence of compressed instruction groupssys, the sequence of compressed instruction groups sys can be restoredby the decoder 156. Accordingly, the processor 102 can execute inparallel, a group of instructions that are the same as the sequence ofinstruction groups before compression. Further, since the sequence ofcompressed instruction groups sys includes compressed instructions, thenumber of fetches from the instruction RAM 151 can be reduced. In otherwords, the number of memory accesses to the instruction RAM 151 can bereduced, thereby enabling reduced power consumption to be facilitated.

Recovery processing from an interrupt occurring during the instructionexecution depicted in FIGS. 43 to 55 will be described. When aninterrupt occurs, the processor 102 completes commit state transitionprocessing (writeback, . . . ) and then performs interrupt processing.In this case, concerning the commit pre-stage processing, the processor102 temporarily saves the value of the lower recovery register 1543 andexecutes the interrupt processing. When the interrupt processing ends,the processor 102 uses the saved value of the lower recovery register1543 and resumes the commit pre-stage processing. Hereinafter, a casewhere an interrupt occurs during the processing depicted in FIG. 55 willbe described with reference to FIGS. 56 to 64.

FIGS. 56 to 64 are diagrams of an example of recovery processing forrecovery from an interrupt. The processor 102, via the interruptcontroller 1510, detects the occurrence of an interrupt by a surroundingmodule or timer and upon doing so, issues via the controller 153, aninterrupt signal to the fetch controller 155, the decoder 156, theexecuting unit 157, and the memory access unit 158.

In FIG. 56, the memory access unit 158, upon receiving the interruptsignal, saves the values of the lower recovery register 1543 or thevalue of a generic register (not depicted) to the stack area 1520 of thedata RAM 152.

In FIG. 57, the fetch controller 155, upon receiving the interruptsignal, clears the prefetch buffer 1551 and the fetch buffer 1552, andprepares for interrupt processing. Similarly, the decoder 156, theexecuting unit 157, and the memory access unit 158, upon receiving theinterrupt signal, respectively clear the values of the upper recoveryregister 1541, the intermediate recovery register 1542, and the lowerrecovery register 1543, and prepare for interrupt processing. Theprocessor 102 executes the interrupt processing.

In FIG. 58, the decoder 156, upon receiving the interrupt completionsignal through the interrupt controller 1510 and the controller 153,sets the lower instruction buffer 32 values (instruction codes A1, F,C1, D1) saved in the stack area 1520, the lower BFI register 33 values(operand patterns A1-BFI, F-BFI, C1-BFI, D1-BFI), and the lowerinstruction counter 34 values “2, 1, 2, 2” to the value of the upperinstruction buffer 12, the value of the upper BFI register 13, and thevalue of the upper instruction counter 14. The fetch controller 155again clears the prefetch buffer 1551 and the fetch buffer 1152, andreads in the lower program counter value “198” saved in the stack area1520.

In FIG. 59, the fetch controller 155 divides the lower program counter31 value “198” read from the stack area 1520, by the bit width (128bits) of the fetch buffer. In this case, the quotient is “1” with aremainder of “70”. The fetch controller 155 multiplies the quotient “1”by the bit width (128 bits) of the fetch buffer and thereby, identifiesthe bit position to be fetched. In this case, since the quotient “1”×128bits=128, the bit string from the 128th bit from the head of thesequence of compressed instruction groups, i.e., the bit string ofaddress 0xFF10 of the instruction RAM 151, is prefetched and held in theprefetch buffer 1551. The fetch controller 155 sets the program counter1553 to “128”.

In FIG. 60, the fetch controller 155 fetches and holds in the fetchbuffer 1552, the bit string in the prefetch buffer 1551. The fetchcontroller 155 determines whether the bit string in the fetch buffer1552 is a non-compressed instruction group. In the case of this bitstring, since the first 4 bits are “1111”, the first 4 bits aredetermined to be compressed instruction groups. In this case, the fetchcontroller 155 transfers the first 4 bits (=1111) in the fetch buffer1552 to the decoder 156.

The fetch controller 155 updates the program counter 1553 by the numberof bits transferred. In this case, since the transferred bit string is 4bits, the value of the program counter 1553 becomes “132”. In this case,since this value and the lower program counter 31 value “198” saved inthe stack area 1520 do not coincide, the fetch controller 155 does nottransfer the updated program counter value “132” to the upper programcounter 11 of the decoder 156.

The decoder 156, despite having received the compressed instructiongroups from the fetch buffer 1552, discards the compressed instructiongroups since the value of the program counter 1553 is not received.Thus, until the value of the program counter 1553 of the fetchcontroller 155 and the lower program counter 31 value read from thestack area 1520 coincide, the decoder 156 discards the bit strings fromthe fetch buffer 1552. As a result, at an errant bit position, theinstruction is not restored.

In FIG. 62, since 4 bits were transferred at the processing depicted inFIG. 61, the fetch controller 155 fetches the first 4 bits of theprefetch buffer 1551. Subsequently, the fetch controller 155 determineswhether the bit string in the fetch buffer 1552 is a non-compressedinstruction. In the case of this bit string, since the first and thethird bits are “1”, the first and the third bits of the fetched bitstring are determined to be compressed instructions.

In FIG. 63, the fetch controller 155 transfers the first 66 bits in thefetch buffer 1552 to the decoder 156. The fetch controller 155 updatesthe program counter 1553 by the number of bits transferred. In thiscase, since the transferred bit string is 66 bits, the value of theprogram counter 1553 becomes “198”. In this case, since this value andthe lower program counter 31 value “198” saved in the stack area 1520coincide, the fetch controller 155 transfers the updated program countervalue “198” to the upper program counter 11 of the decoder 156.

In FIG. 64, the decoder 156, having received the bit string from thefetch buffer 1552 and the program counter 1553 value “198”, restores theinstructions from the values of the upper recovery register 1541. Thus,the instruction codes A3, C3 that were processed up to the memory accessunit 158 at the time of the interrupt are restored. The processinghereinafter is executed similarly to that depicted in FIGS. 51 to 55.Thus, at the proper recovery position, the instruction can be restored.

In this manner, according to the second embodiment, since an instructionsequence/a sequence of instruction groups that include compressedinstructions can be restored while being executed, the number of fetchesfrom the instruction RAM 151 can be reduced. The number of fetches fromthe instruction RAM 151 becomes shorter than the original instructionsequence/sequence of instruction groups, the higher the instructioncompression efficiency, i.e., the greater the number of compressedinstructions is. For example, in the case of the third embodiment, sincea maximum of 32 compressed instructions can be acquired by 1 fetchingand consequently, 32×32 non-compressed instructions (1024 bits) arefetched by 1 memory access.

Further, in the case of the fourth embodiment, since a maximum of 32compressed instruction groups can be acquired by 1 fetching, 32×32non-compressed instruction groups (1024 bits) are fetched by 1 memoryaccess. Therefore, since the number of accesses to the instruction RAM151 decreases, reduced power consumption is enabled.

Further, when transitioning to the subsequent stage at each stage ofcommit pre-stage, the processor 102 also passes, by pipeline processing,the recovery register values to the subsequent stage. Consequently, evenif an interrupt occurs during execution, by saving the value of therecovery register at the memory access of the last stage of commitpre-stage, recovery can be performed using the saved recovery registervalue, after the completion of the interrupt. Thus, even if aninstruction sequence/a sequence of instruction groups that are to beexecuted are also compressed, by indicating the instruction that isbefore transition to the commit state and re-executing from aninstruction fetch, the state before the interrupt can be recovered.

Further, according to second embodiment, when a compressed instructionis restored, since restoration is performed within the processor 102 andwithout access to an external memory such as a dictionary memory,excessive memory accesses become unnecessary and there is no increase inthe number of memory accesses. Therefore, reduced power consumption canbe facilitated. Further, when the same operation code occurssuccessively, since coding in which register numbers and/or memoryaddresses (which are operands) consecutively numbered is used, when aprogrammer creates instruction code, by varying the operands in aconsistent manner when the same operation code occurs successively,reduced power consumption at the time of instruction compression andexecution can be facilitated.

In the second embodiment, although the restoration of instruction codewas described to be performed at a register read stage by the decoder156, the restoration at register read may be performed at a fetch stage.In this case, the upper recovery register 154 and the operand updater1600 are included in the fetch controller 155; and the data holding andreading performed with respect to the upper recovery register 154 at theregister read stage in the operand updating processing by the operandupdater 1600 is executed by the fetch controller 155. Further, in thiscase, the decoder 156 performs typical decoder processing and readingfrom data registers.

As described, the processor 102 according to the embodiments reduces thenumber of memory accesses by collectively fetching a sequence ofcompressed instructions in a memory. Further, the compression apparatus,the compression method, and the computer product improve the efficiencyat which an instruction code group is compressed consequent to areduction in the number of memory accesses by the processor 102.

The compression method described in the present embodiment may beimplemented by executing a prepared program on a computer such as apersonal computer and a workstation. The program is stored on acomputer-readable medium such as a hard disk, a flexible disk, a CD-ROM,an MO, and a DVD, read out from the recording medium, and executed bythe computer. The program may be distributed through a network such asthe Internet. However, the computer-readable medium does not include atransitory medium such as a propagation signal.

All examples and conditional language recited herein are intended forpedagogical purposes to aid the reader in understanding the inventionand the concepts contributed by the inventor to furthering the art, andare to be construed as being without limitation to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although the embodiments of the presentinvention have been described in detail, it should be understood thatthe various changes, substitutions, and alterations could be made heretowithout departing from the spirit and scope of the invention.

What is claimed is:
 1. A processor having access to a memory storingtherein a sequence of compressed instruction groups includingcompression information indicating that an instruction having operationcode identical to that of the preceding instruction and having operandcontinuity with the preceding instruction has been compressed, theprocessor comprising: a fetcher that fetches a given bit string from thememory and judges a combination pattern of the compression informationin the given bit string and a non-compressed instruction, whereconcerning a non-compressed instruction, further identifies thenon-compressed instruction in the given bit string and transfers thenon-compressed instruction, and concerning the compression information,further transfers the compression information, and a decoder that uponreceiving the non-compressed instruction transferred thereto from thefetcher, holds in a buffer, instruction code and an operand pattern ofthe non-compressed instruction and executes setting processing ofsetting to an initial value, the value of an instruction counter thatindicates a consecutive count of consecutive instructions havingidentical operation code and operands with regularity, and uponreceiving the compression information transferred thereto from thefetcher, restores the instruction code based on the instruction codeheld in the buffer, the value of the instruction counter, and theoperand pattern.
 2. A computer-readable medium storing therein acompression program that causes a computer to execute a process, theprocess comprising: acquiring a test subject from an instruction groupunder test that is among a sequence of instruction groups; determiningwhether operation code of the acquired test subject and operation codeof a preceding instruction are identical, and whether operands of thetest subject and operands of the preceding instruction have continuity,the preceding instruction being an instruction at a position thatcorresponds to that of the test subject, in the instruction group thatprecedes the instruction group under test; and compressing the testsubject when at the determining identicalness and continuity aredetermined.
 3. The computer-readable medium according to claim 2,wherein the compressing, when identicalness and continuity aredetermined, includes appending to the test subject, compressioninformation indicating that the test subject is compressed, and deletingthe operation code and the operands of the test subject.
 4. Thecomputer-readable medium according to claim 2, the process furthercomprising setting for the test subject, compression informationindicating that the test subject is not compressed and storageinformation indicating that the test subject is an instruction that isto be stored, the setting being performed when identicalness andcontinuity are not determined at the determining.
 5. Thecomputer-readable medium according to claim 4, wherein the determining,when identicalness and continuity are not determined, includesdetermining whether the test subject is to be stored, based on theoperation code type of the test subject, and the setting, when storageis determined, includes setting for the test subject, the compressioninformation indicating that the test subject is not compressed and thestorage information indicating that the test subject is an instructionthat is to be stored, and when storage is not determined, includessetting for the test subject, compression information indicating thatthe test subject is not compressed and the storage informationindicating that the test subject is not an instruction that is to bestored.
 6. The computer-readable medium according to claim 2, theprocess further comprising storing a compression information groupobtained from test subjects of the instruction group under test, andsubsequent to the compression information group, storing anon-compressed test subject that is in the instruction group under test,is not compressed, and for which the storage information has been set.7. The computer-readable medium according to claim 6, wherein thestoring includes shortening by concatenating storage results obtainedfor each instruction group under test.
 8. A compression apparatuscomprising: an acquirer that acquires a test subject from an instructiongroup under test that is among a sequence of instruction groups; adeterminer that determines whether operation code of the acquired testsubject and operation code of a preceding instruction are identical, andwhether operands of the test subject and operands of the precedinginstruction have continuity, the preceding instruction being aninstruction at a position that corresponds to the that of the testsubject, in the instruction group that precedes the instruction groupunder test; and a compressor that compresses the test subject whenidenticalness and continuity are determined by the determiner.
 9. Acompression method executed by a computer, the compression methodcomprising: acquiring a test subject from an instruction group undertest that is among a sequence of instruction groups; determining whetheroperation code of the acquired test subject and operation code of apreceding instruction are identical, and whether operands of the testsubject and operands of the preceding instruction have continuity, thepreceding instruction being an instruction at a position thatcorresponds to that of the test subject, in the instruction group thatprecedes the instruction group under test; and compressing the testsubject when at the determining identicalness and continuity aredetermined.